Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A semiconductor device includes an oxide-nitride-oxide (ONO) dielectric stack on a surface of a substrate, and a high work function gate electrode formed over a surface of the ONO dielectric stack. The ONO dielectric stack includes a multi-layer charge storage layer including a silicon-rich, oxygen-lean top silicon nitride layer and an oxygen-rich bottom silicon nitride layer. The high work function gate electrode includes a P+ doped polysilicon layer.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A method of forming a transistor is described. In one embodiment the method includes: forming a channel of a transistor in a surface of a substrate; forming a dielectric stack including a first oxide layer overlying the surface of the substrate, a middle layer comprising nitride overlying the first oxide layer and a second oxide layer overlying the middle layer; forming over the dielectric stack a mask exposing source and drain (S/D) regions of the transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the second oxide layer and at least a first portion of the middle layer in S/D regions of the transistor; and implanting dopants into S/D regions of the transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the channel of the transistor. Other embodiments are also described.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described.

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract: A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer; and a gate electrode comprising doped polysilicon formed over a surface of the ONNO stack. The MOS logic transistor includes a gate oxide and a gate electrode comprising doped polysilicon. Other embodiments are also described.

Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.

Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.

Abstract: Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. A gate stack overlies the channel, the gate stack comprising a tunneling layer, a trapping layer, a blocking layer, a gate layer; and a deuterated gate cap layer. The gate cap layer has a higher deuterium concentration at an interface with the gate layer than at surface of the gate cap layer distal from the gate layer. In certain embodiments, the channel comprises polysilicon or recrystallized polysilicon. Other embodiments are also described.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.

Abstract: A semiconductor device includes an oxide-nitride-oxide (ONO) dielectric stack on a surface of a substrate, and a high work function gate electrode formed over a surface of the ONO dielectric stack. The ONO dielectric stack includes a multi-layer charge storage layer including a silicon-rich, oxygen-lean top silicon nitride layer and an oxygen-rich bottom silicon nitride layer. The high work function gate electrode includes a P+ doped polysilicon layer.

Abstract: A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.