Patents by Inventor KUN-MU LI
KUN-MU LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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EPITAXIAL FIN STRUCTURES OF FINFET HAVING AN EPITAXIAL BUFFER REGION AND AN EPITAXIAL CAPPING REGION
Publication number: 20240088266Abstract: A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Chang SUNG, Kun-Mu LI -
Patent number: 11916071Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.Type: GrantFiled: February 23, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu, Tsz-Mei Kwok
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Epitaxial fin structures of finFET having an epitaxial buffer region and an epitaxial capping region
Patent number: 11888046Abstract: A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.Type: GrantFiled: November 1, 2021Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Chang Sung, Kun-Mu Li -
Publication number: 20230369491Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a gate structure arranged over a substrate and a source/drain region arranged within the substrate along a side of the gate structure. The source/drain region includes a first layer lining interior sidewalls and a horizontally extending surface of the substrate, and a second layer lining interior sidewalls and a horizontally extending surface of the first layer. The first layer has a dopant with a first dopant concentration that continually decreases from an outermost sidewall of the first layer facing the substrate to one of the interior sidewalls of the first layer.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Publication number: 20230352589Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Patent number: 11749752Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.Type: GrantFiled: December 3, 2020Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Patent number: 11735664Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: GrantFiled: August 30, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Publication number: 20230231052Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Inventors: Kun-Mu Li, Hsueh-Chang Sung
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Publication number: 20230124966Abstract: A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.Type: ApplicationFiled: December 21, 2022Publication date: April 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing LEE, Tsz-Mei KWOK, Ming-Hua YU, Kun-Mu LI
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Publication number: 20230113464Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure, and a source/drain structure in the fin structure and adjacent to the gate structure. The source/drain structure includes: a first epitaxial layer over the fin structure, a second epitaxial layer over the first epitaxial layer, and an epitaxial capping layer over the second epitaxial layer. The semiconductor structure also includes a silicide layer formed in contact with the source/drain structure. The silicide layer has a curved bottom surface, and the curved bottom surface of the silicide layer intersects with the second epitaxial layer and the epitaxial capping layer.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kun-Mu LI, Wei-Yang LEE, Wen-Chu HSIAO
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Patent number: 11610994Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.Type: GrantFiled: March 12, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kun-Mu Li, Hsueh-Chang Sung
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Publication number: 20230049249Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Inventors: Kun-Mu LI, Tsz-Mei KWOK, Ming-Hua YU, Chan-Lon YANG
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Patent number: 11574916Abstract: A method for manufacturing a semiconductor device includes etching a substrate to form a semiconductor fin. An isolation structure is formed above the substrate and laterally surrounds the semiconductor fin. A fin sidewall structure is formed above the isolation structure and on a sidewall of the semiconductor fin. The semiconductor fin is recessed to expose an inner sidewall of the fin sidewall structure. A source/drain epitaxial structure is grown on the recessed semiconductor fin.Type: GrantFiled: November 4, 2020Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
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Patent number: 11532749Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.Type: GrantFiled: December 11, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Mu Li, Wei-Yang Lee, Wen-Chu Hsiao
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Patent number: 11489074Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.Type: GrantFiled: August 17, 2020Date of Patent: November 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Mu Li, Tsz-Mei Kwok, Ming-Hua Yu, Chan-Lon Yang
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Patent number: 11437515Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.Type: GrantFiled: July 10, 2020Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Patent number: 11411109Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.Type: GrantFiled: February 8, 2021Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
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Publication number: 20220238709Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
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Publication number: 20220181320Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.Type: ApplicationFiled: February 23, 2022Publication date: June 9, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing LEE, Kun-Mu LI, Ming-Hua YU, Tsz-Mei KWOK
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Patent number: 11355500Abstract: A static random access memory (SRAM) cell includes a semiconductor fin, a first gate structure, a second gate structure, an epitaxy structure, and a first fin sidewall structure. The first gate structure crosses the semiconductor fin to form a pull-down (PD) transistor. The second gate structure crosses the semiconductor fin to form a pull-gate (PG) transistor. The epitaxy structure is on the semiconductor fin and between the first and second gate structures. The first fin sidewall structure is on a first side of the epitaxy structure and between the first and second gate structures. A method for manufacturing the semiconductor device is also disclosed.Type: GrantFiled: July 13, 2020Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li