Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes forming first and second semiconductor fins; forming first and second dielectric fin sidewall structures on opposite sidewalls of the first semiconductor fin, wherein the first dielectric fin sidewall structure is higher than the second dielectric fin sidewall structure, and the second dielectric fin sidewall structure is between the first and second semiconductor fins; recessing at least a portion of the first semiconductor fin between the first and second dielectric fin sidewall structures until a top of the recessed portion of the first semiconductor fin is lower than a top of the first dielectric fin sidewall structure; and forming a first epitaxy structure on the recessed portion of the first semiconductor fin.

Abstract: A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.

Abstract: A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region.

Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium con

Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium con

Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Abstract: A method for manufacturing a semiconductor device includes etching a substrate to form a semiconductor fin. An isolation structure is formed above the substrate and laterally surrounds the semiconductor fin. A fin sidewall structure is formed above the isolation structure and on a sidewall of the semiconductor fin. The semiconductor fin is recessed to expose an inner sidewall of the fin sidewall structure. A source/drain epitaxial structure is grown on the recessed semiconductor fin.

Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

Abstract: A semiconductor device, and a method of manufacturing, is provided. A first recess in the semiconductor layer may be disposed between a first dummy gate and a second dummy gate. A first spacer is formed on sidewalls of the first dummy gate and a second spacer is formed on sidewalls of the second dummy gate. The first and second spacers form triangular spacer extensions contacting the bottom surface of the first recess. After forming the first spacer and the second spacer, a second recess is formed in the semiconductor layer disposed between the first dummy gate and the second dummy gate. A source/drain region is epitaxially grown in the second recess.

Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium con

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.