Patents by Inventor KUN-MU LI
KUN-MU LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190131310Abstract: A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.Type: ApplicationFiled: December 27, 2018Publication date: May 2, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing LEE, Tsz-Mei KWOK, Ming-Hua YU, Kun-Mu LI
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Publication number: 20190123201Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.Type: ApplicationFiled: December 19, 2018Publication date: April 25, 2019Inventors: Kun-Mu LI, Tsz-Mei KWOK, Ming-Hua YU, Chan-Lon YANG
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Patent number: 10269648Abstract: Methods of fabricating a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes epitaxially growing a source/drain structure covering the fin structure. In addition, the method includes epitaxially growing a capping layer over the source/drain structure. The capping layer has a top portion and a lower portion under the top portion. The top portion has a first thickness and the lower portion has a second. A ratio of the first thickness to the second thickness is in a range of about 1.01 to about 2. The method also includes etching the top portion and the lower portion of the capping layer. The method further includes forming a silicide layer over the source/drain structure and a contact over the silicide layer.Type: GrantFiled: December 28, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Mu Li, Chih-Chiang Chang, Wen-Chu Hsiao
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Publication number: 20190115470Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.Type: ApplicationFiled: December 7, 2018Publication date: April 18, 2019Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Publication number: 20190097006Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.Type: ApplicationFiled: August 13, 2018Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Mu LI, Wei-Yang LEE, Wen-Chu HSIAO
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Publication number: 20190035931Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.Type: ApplicationFiled: September 24, 2018Publication date: January 31, 2019Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20190013405Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.Type: ApplicationFiled: August 27, 2018Publication date: January 10, 2019Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
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Patent number: 10170483Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.Type: GrantFiled: September 12, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
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Patent number: 10164096Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.Type: GrantFiled: August 21, 2015Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Mu Li, Ming-Hua Yu, Tsz-Mei Kwok, Chan-Lon Yang
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Publication number: 20180366373Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Mu LI, Chih-Chiang Chang, Wen-Chu Hsiao, Che-Yu Lin, Wei-Siang Yang
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Patent number: 10158016Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.Type: GrantFiled: March 6, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Patent number: 10103064Abstract: The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers.Type: GrantFiled: May 28, 2014Date of Patent: October 16, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
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Patent number: 10084089Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.Type: GrantFiled: September 5, 2017Date of Patent: September 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Patent number: 10062781Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.Type: GrantFiled: November 13, 2017Date of Patent: August 28, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
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Patent number: 10026662Abstract: A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have a first height, and a first epitaxy structure is disposed in the first fin structure, which a portion of the first epitaxy structure is above the first fin spacers and having a first width. In the test region, second fin spacers cover sidewalls of the second fin structure and have a second height, and the second height is greater than the first height. A second epitaxy structure is disposed in the second fin structure, and a portion of the second epitaxy structure is above the second fin spacers and having a second width, which the second width is less than the first width.Type: GrantFiled: November 6, 2015Date of Patent: July 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsueh-Chang Sung, Chih-Chiang Chang, Kun-Mu Li
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Publication number: 20180190810Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.Type: ApplicationFiled: October 4, 2017Publication date: July 5, 2018Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
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Patent number: 10014411Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.Type: GrantFiled: May 11, 2016Date of Patent: July 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20180175031Abstract: An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins. The first epitaxy structure and the second epitaxy structure are merged together. The first and second dielectric fin sidewall structures are respectively on opposite first and second sidewalls of the first epitaxy structure. The first sidewall of the first epitaxy structure faces the second epitaxy structure. The first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing LEE, Kun-Mu LI, Ming-Hua YU, Tsz-Mei KWOK
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Patent number: 9991364Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.Type: GrantFiled: June 2, 2017Date of Patent: June 5, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
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Publication number: 20180151698Abstract: A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region.Type: ApplicationFiled: April 28, 2017Publication date: May 31, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Chang Sung, Kun-Mu Li