Abstract: A semiconductor light emitting device includes a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, a first electrode disposed below the light emitting structure, the first electrode being electrically connected to the first conductivity type semiconductor layer, a second electrode within the light emitting structure, the second electrode being electrically connected to the second conductivity type semiconductor layer, an insulating part electrically separating the second electrode from the first conductivity type semiconductor layer, the active layer, and the first electrode, a first pad electrode electrically connected to the first electrode, and a second pad electrode electrically connected to the second electrode, the second pad electrode being exposed to a top surface of the light emitting structure.

Abstract: Provided are a circuit board for irradiating light to a light guide plate and a flat panel display having a structure for efficiently fixing the circuit board and the light guide plate, the circuit board, including: a support substrate comprising a first area and a second area, the second area being bent from the first area; a plurality of light emitting device mounting parts disposed in the first area; and a protective member connecting part of an outer side of the plurality of light emitting device mounting parts.

Abstract: A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.

Abstract: A three dimensional non-volatile memory structure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.

Abstract: Provided is a printed circuit board including: a support substrate including a first area in which a light emitting device is mounted, and a second area extending from the first area; a bending part which is configured such that a part between the first area and the second area is bent; a through hole passing through the bending part; a connection wiring connected to the light emitting device and disposed on the bending part; and a wiring connected to the connection wiring.

Abstract: Provided is an X-ray detecting device including a scintillator panel, an adhesive layer, an imaging device panel, and so on. The scintillator panel includes a substrate through which an X-ray passes, a reflective layer formed on the substrate and configured to allow penetration of the X-ray and reflect visible light, and a scintillator layer formed on the reflective layer and configured to convert the X-ray into the visible light. The adhesive layer is formed on the scintillator layer of the scintillator panel. The imaging device panel is coupled on the adhesive layer and has a plurality of light receiving elements and a plurality of electrode pads installed at a surface thereof directed toward the adhesive layer.

Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Abstract: A scintillator panel includes a substrate, a reflection layer, a scintillator layer and a transmission oxide layer. The substrate transmits the X-ray. The reflection layer is formed on the substrate to transmit the X-ray and reflect the visible light. The scintillator layer is formed on the reflection layer to convert the X-ray into the visible light. And, the oxide layer seals the scintillator layer, transmits the visible light and blocks the penetration of moisture.

Abstract: A scintillator panel includes a scintillator layer to be formed on an imaging device and an oxide layer on the scintillator layer to transmit an X-ray, reflect a visible light, and prevent moisture from being penetrated. The oxide layer has a structure including a number of oxide layers.

Abstract: Disclosed herein are a variable resistance memory device and a method of fabricating the same. The variable resistance memory device may include a first electrode; a second electrode; and a variable resistance layer configured to be interposed between the first electrode and the second electrode, wherein the variable resistance layer includes a Si-added metal oxide.

Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.

Abstract: The present description relates to an apparatus and method for receiving a control channel in a multi-component carrier system. The method for performing random access disclosed in the present description comprises the steps of: transmitting a random access preamble to a base station from an activated sub-serving cell; monitoring physical downlink control channel candidates during a response window one the basis of a certain aggregation in a temporary search space in a control region of the activated sub-serving cell, wherein the control region consists of a group of control channel elements; and adjusting an uplink time of the activated sub-serving cell according to a time advance command indicated by a random access response when the random access response, including a random access identifier corresponding to the random access preamble, is received in the response window.

Abstract: A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.

Abstract: A method for forming a silicon oxide film of a semiconductor device is disclosed. The method of forming the silicon oxide film of the semiconductor device includes performing surface processing using an amine-based compound, so that the uniformity and density of the silicon oxide film may be improved.

Abstract: A semiconductor light emitting device includes a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first internal electrode, a second internal electrode, an insulating part, and first and second pad electrodes. The active layer is disposed on a first portion of the first conductive semiconductor layer, and has the second conductive layer disposed thereon. The first internal electrode is disposed on a second portion of the first conductive semiconductor layer separate from the first portion. The second internal electrode is disposed on the second conductive semiconductor layer. The insulating part is disposed between the first and second internal electrodes, and the first and second pad electrodes are disposed on the insulating part to connect to a respective one of the first and second internal electrodes.

Abstract: A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.

Abstract: The present invention relates to a method and an apparatus for dynamically configuring a resource allocation unit within a PDCCH for an effective resource allocation of multiple cell or multiple component carriers, the method comprising the steps of: configuring at least one carrier in a terminal; and transmitting, using a single control channel, resource allocation information for indicating resource blocks concatenated to at least one component carrier and allocated as data channels, wherein the resource allocation information comprises information about the size of a resource block group which defines the basic unit of allocation for the concatenated resource blocks.

Abstract: A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor.

Abstract: A resistive memory device operable with low power consumption and a memory apparatus and data processing system including the same are provided. The resistive memory includes a chalcogenide compound containing 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te).

Abstract: A semiconductor light emitting element includes a light emitting structure including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer. A first electrode structure includes a conductive via connected to the first conductivity type semiconductor layer. A second electrode structure is connected to the second conductivity type semiconductor layer. An insulating part having an open region exposes part of the first and second electrode structures while covering the first and second electrode structures. First and second pad electrodes are formed on the first and second electrode structures exposed by the open region and are connected to the first and second electrode structures.