Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.

Abstract: Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

Abstract: Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

Abstract: A pre-cut glass body is employed as a separator between an anode current collector and a cathode current collector of a micro-battery. The use of a pre-cut glass body in micro-battery applications provides excellent insulation for the micro-battery and can also result in enhanced battery reliability and lifetime.

Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.

Abstract: A multi-layer wafer and method of manufacturing such wafer are provided. The method includes applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.

Abstract: A technique relates to a semiconductor device. First nanowires are formed on a first substrate, the first nanowires being electrically coupled to one or more first electrical sites on the first substrate. Second nanowires are formed on a second substrate, the second nanowires being electrically coupled to one or more second electrical sites on the second substrate. The first nanowires and the second nanowires are electrically coupled such that the one or more first electrical sites are electrically coupled to the one or more second electrical sites.

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

Abstract: Apparatus, systems, and methods for determining a temperature excursion are provided. In one example, a system can comprise a temperature switch component that experiences a temperature excursion associated with a metal alloy of the temperature switch component and one or more electrodes, wherein the temperature excursion is based on a temperature of the metal alloy exceeding a defined threshold value. Additionally, the system can comprise a radio frequency identification tag component that receives a signal, from an external reader device, utilized to determine that the temperature excursion has occurred based on a parameter change, associated with the temperature excursion, from a first parameter to a second parameter different than the first parameter.

Abstract: A thermal tag for activity monitoring. The thermal tag includes a base layer having a plurality of metal lines to provide a conductive path, and a pattern layer having one or more infrared emitting features positioned over portions of the conductive path, wherein at least one infrared emitting feature couples to the conductive path to emit a predetermined infrared pattern in accordance with nearby activity.

Abstract: Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

Abstract: A bonded structure contains a substrate containing at least one feature, the substrate having a top surface; a first release layer overlying the top surface of the substrate, the first release layer being absorptive of light having a first wavelength for being decomposed by the light; an adhesive layer overlying the first release layer, and a second release layer overlying the adhesive layer. The second release layer is absorptive of light having a second wavelength for being decomposed by the light having the second wavelength. The bonded structure further contains a handle substrate that overlies the second release layer, where the handle substrate is substantially transparent to the light having the first wavelength and the second wavelength. Also disclosed is a debonding method to process the bonded structure to remove and reclaim the adhesive layer for re-use. In another embodiment a multi-step method optically cuts and debonds a bonded structure.

Abstract: A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

Abstract: A thermal tag for activity monitoring. The thermal tag includes a base layer having a plurality of metal lines to provide a conductive path, and a pattern layer having one or more infrared emitting features positioned over portions of the conductive path, wherein at least one infrared emitting feature couples to the conductive path to emit a predetermined infrared pattern in accordance with nearby activity.

Abstract: A device wafer is bonded to a handle by a low temperature adhesive bond material that includes a suspended polymer with glass transition temperature greater than room temperature and a diluent polymer that is curable to provide a thermoset polymer upon exposure to ultraviolet radiation, x-ray radiation and/or thermal treatments at low temperature. The suspended polymer and the diluent polymer are mixed to a consistency such that before curing of the diluent polymer the low temperature adhesive bond material exhibits adhesion strength less than 10 Newtons per square centimeter (N/cm2), and after curing of the diluent polymer the low temperature adhesive bond material exhibits adhesion strength not less than about 40 N/cm2.

Abstract: A method of manufacturing a multi-layer wafer is provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The the at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Abstract: A thermal tag includes a power source to generate current along a resistive path and a plurality of infrared-emitting features positioned along the resistive path to emit infrared light along an infrared-emitting pattern, wherein the plurality of infrared-emitting features include one or more infrared-emitting stripes on a first surface of the thermal tag defining a pattern region and a plurality of infrared-emitting dots within a portion of the pattern region to provide a thermal-diffusion resistant pattern for activity monitoring.