Abstract: A fault detection method includes: obtaining a video quality parameter of a monitored video stream, where the video quality parameter is determined according to a packet loss recovery method of the monitored video stream, the video quality parameter includes an effective packet loss factor, and the effective packet loss factor is used to indicate effectiveness of network packet loss recovery performed by using the packet loss recovery method of the monitored video stream; and performing fault detection based on the video quality parameter of the monitored video stream.

Abstract: A computer-implemented method for ordinal prediction is provided. The method includes encoding time series data with a temporal encoder to obtain latent space representations. The method includes optimizing the temporal encoder using semi-supervised learning to distinguish different classes in the labeled space using labeled data, and augment the latent space representations using unlabeled training data, to obtain semi-supervised representations. The method further includes discarding a linear layer after the temporal encoder and fixing the temporal encoder. The method also includes training k?1 binary classifiers on top of the semi-supervised representations to obtain k?1 binary predictions. The method additionally includes identifying and correcting inconsistent ones of the k?1 binary predictions by matching the inconsistent ones to consistent ones of the k?1 binary predictions. The method further includes aggregating the k?1 binary predictions to obtain an ordinal prediction.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

Abstract: Provided are a continuous post-treatment method and device for a penem compound. The method includes the following steps: S1, performing continuous extraction on a reaction crude product of a penem compound, to obtain an extraction heavy phase and an extraction light phase; S2, performing continuous solid-liquid separation on the extraction heavy phase, to obtain a liquid phase separation product; S3, performing continuous pH adjustment on the liquid phase separation product until a pH value thereof is 6.1-6.3, to obtain pH-adjusted solution; and S4, performing continuous crystallization treatment on the pH-adjusted solution by a first crystallization solvent, to obtain a penem compound product. The use of the method for the post-treatment of the reaction crude product of the penem compound has the advantages of high treatment speed and high efficiency, and stable material properties and a low deterioration rate during the treatment, and has better control over the yield and purity of a target product.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: Provided is a peptide and method in preventing or treating infections caused by a wide spectrum of pathogens, including bacteria and fungus in hosts such as plants and animals. Methods of preventing or treating plant diseases and infection in animals are also provided.

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

Abstract: A client determines that a user is attempting to access media program recommendations. In response to the determination, the client attempts to collect media program recommendations to be presented to the user. Media program recommendations may be derived locally by the client, by the client and a multimedia device locally connected with the client, by the client and one or more additional devices, etc. In some embodiments, in response to receiving a query from the client, one or more recipient devices or servers identify media program recommendations in a plurality of trending categories. The media program recommendations may be selected based at least in part on EPG data and audience research and measurement data. The media program recommendations collected by the client are presented to the user for further exploration. The client may be one of mobile phones, tablet computers, etc.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: Systems, methods, and processor-readable media for elastic allocation of resources for deep learning jobs are described. A machine-learning-as-a-service (MLaaS) of a cloud computing system includes an elastic training module which includes resource allocator for allocating resources to training jobs that optimizes overall estimated time to completion (ETC) for all training jobs received by the system and uses node-based resource allocation. The elastic training module may realize a combination of high resource utilization, short training times, and low queueing delay relative to existing approaches, thereby potentially enabling the realization of higher profits for a cloud computing system which provides MLaaS to users (i.e. customers). An improved user interface is described, enabling users to specify a range of resources to elastically allocate to the user's training job, and/or informing users of training time saved through the use of elastic resource allocation.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Abstract: A USB active optical cable and a plug capable of managing power consumption and state. The USB active optical cable and plug respectively comprises a first plug, a second plug, and an optical transmission medium used to connect the first plug and the second plug; the first plug and the second plug are configured to operate different operating states, including an initialization mode, a transmission mode, and a power saving mode, and they can switch between the different operating states. The USB active optical cable and plug are both based on the separate control of the transmitting unit and the receiving unit to distinguish different operating modes, provide necessary operating requirements and mode switching conditions for each mode, and also enable the checking and transmission of the plugging state in the power saving mode, thus facilitate the power consumption management of the active optical cable.

Abstract: A data processing method, apparatus and system are disclosed. The method includes: splitting a preset data processing module from a machine learning model, to generate a security application module configured for performing encryption calculation on data input into the machine learning model; taking, through a preset operator, an output value of an operation layer in the split machine learning model as an input value to be input into the security application module, and inputting the input value into the security application module; performing, through the security application module, subgraph calculation in an isolated operating environment according to the input value, to obtain a calculation result; returning the calculation result to the preset operator. The present application solves the technical problem of high computational pressure of TEE model due to that different reasoning frameworks need to be adapted to different customer requirements in the TEE model in related technologies.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a transistor region in a substrate; forming a gate dielectric layer over the transistor region; forming a diffusion-blocking layer over the gate dielectric layer; forming a first portion of a work function layer over the diffusion-blocking layer; forming a second portion of the work function layer over the first portion of the work function layer; forming a plurality of barrier elements on or under a top surface of the second portion of the work function layer; and forming a gate electrode over the work function layer, wherein the plurality of barrier elements block oxygen from diffusing into the work function layer during the formation of the gate electrode.

Abstract: Anti-PVRIG and anti-TIGIT antibodies are provided.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.