Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

Abstract: A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process. The process system then uses the selected process conditions data for the next etching process.

Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

Abstract: A display device includes a display, at least one light emitting element and at least one reflector. The display has a display surface and a back surface opposite to each other, and the display surface faces a front of the display. The light emitting element is disposed on the back surface. The reflector is slidably connected to the back surface and has a reflecting surface. When the reflector slides to a first position, the reflecting surface is hidden. When the reflector slides to a second position, the reflecting surface is exposed, such that light emitted from the light emitting element is reflected toward the front of the display by the reflecting surface.

Abstract: A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.

Abstract: A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.

Abstract: A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.

Abstract: The present invention discloses a polyether derivative and a preparation method therefor. The polyether derivative is: the polyether derivative of the present invention has a functional group introduced into the polyether chain, such that the derivative has an ether bond, an ester group, an amino group, a heteroatom, and other groups, enabling the derivative to have various functions such as anti-oxidation, anti-wear functionality, and anti-rust functionality, either without requiring additional additives or requiring fewer additional additives used to make up for the lack of base oil functions.

Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.

Abstract: A package structure is provided. The package structure includes a leadframe, a GaN power device, and an electrostatic discharge protection component. The leadframe includes a gate pad, a source pad, and a drain pad, which are disposed on the leadframe. The GaN power device has a gate end. The GaN power device is disposed on the source pad of the leadframe. The electrostatic discharge protection component includes a first pad. The first pad is disposed on the electrostatic discharge protection component. The electrostatic discharge protection component is disposed on the source pad of the leadframe. The gate end of the GaN power device is electrically connected to the first pad of the electrostatic discharge protection component. The first pad of the electrostatic discharge protection component is electrically connected to the gate pad of the leadframe.

Abstract: An image processing method includes obtaining a reflective picture, superimposing the reflective picture on an icon, and changing a color value of at least one pixel in a part that is of the reflective picture and that overlaps the icon.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

Abstract: A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.

Abstract: A thin-film deposition system deposits a thin-film on a wafer. A radiation source irradiates the wafer with excitation light. An emissions sensor detects an emission spectrum from the wafer responsive to the excitation light. A machine learning based analysis model analyzes the spectrum and detects contamination of the thin-film based on the spectrum.

Abstract: An anti-curling film is provided. The anti-curling film includes a first portion and a second portion covering the first portion. The first portion includes polylactic acid (PLA), polycaprolactone (PCL), polyethylene glycol dimethacrylate (PEGDMA) and a photoinitiator. The second portion includes polycaprolactone (PCL), gelatin, hyaluronic acid (HA), alginate (AA), polyvinyl alcohol (PVA) or a combination thereof.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure may include a logic device disposed, at a first side of the logic device, on a carrier wafer of the semiconductor structure. The semiconductor structure may include a dielectric structure disposed on a second side of the logic device, the second side being opposite the first side. The semiconductor structure may include a memory device formed on the dielectric structure.

Abstract: A client determines that a user is attempting to access media program recommendations. In response to the determination, the client attempts to collect media program recommendations to be presented to the user. Media program recommendations may be derived locally by the client, by the client and a multimedia device locally connected with the client, by the client and one or more additional devices, etc. In some embodiments, in response to receiving a query from the client, one or more recipient devices or servers identify media program recommendations in a plurality of trending categories. The media program recommendations may be selected based at least in part on EPG data and audience research and measurement data. The media program recommendations collected by the client are presented to the user for further exploration. The client may be one of mobile phones, tablet computers, etc.

Abstract: A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.