Abstract: A method includes selecting a particular ready/busy pin (R/B#) among a plurality of R/B# pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B# pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

Abstract: A securing clip includes: an enclosure body including a first end, a second end, and one or more sidewalls that extend between the first end and the second end; one or more fragment module securing tangs extending, from one or more of the sidewalls, into the cavity such that when at least a portion of the fragment module is placed within the cavity, at least a portion of the fragment module securing tang is designed to engage with the fragment module and prevents and/or impedes removal of at least a portion of the fragment module from the cavity; and one or more substrate securing tangs extending from the enclosure body and away from the cavity, each substrate securing tang designed to prevent and/or impede removal of the securing clip when the securing clip is placed into a substrate aperture defined within the substrate

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods that utilize a specially trained machine-learning model to generate an emerging user segment based on a target outcome for digital survey responses and respondent attributes of respondents to such digital surveys. In some cases, for instance, the emerging user segment includes a group of users that share the same or similar characteristics as the subset of respondents. By analyzing respondent attributes of digital survey respondents that match a target outcome, the disclosed systems can use the specially trained machine-learning model to dynamically predict users that likely have (or are at risk of having) the same or a similar target outcome—even if such users did not respond to the relevant digital survey.

Abstract: A method for producing a crystalline film comprising zeolite and/or zeolite-like crystals on a porous substrate is described. The method has the steps of: providing a porous support; modifying at least a surface of the top-layer of said porous support by treatment with a composition having one or more cationic polymer(s); rendering at least the outer surface of said porous support hydrophobic by treatment with a composition having one or more hydrophobic agent(s); subjecting said treated porous support to a composition having zeolite and/or zeolite-like crystals thereby depositing and attaching zeolite and/or zeolite-like crystals on said treated porous support, and growing a crystalline film of zeolite and/or zeolite-like crystals on said treated porous support and calcination. Crystalline films find use in a variety of fields such as in the production of membranes, catalysts etc.

Abstract: A variety of applications can include multiple memory die packages configured to engage in peak power management (PPM) across the multiple packages of memory dies. A communication line coupled to each memory die in the multiple memory die packages can be used to facilitate the PPM. A global management die can start a communication sequence among the multiple memory die packages to share a current budget across the multiple memory die packages by driving a signal on the communication line. Local management dies can use the received signal having clock pulses driven by the global management die on the communication line to engage in the PPM. To engage in global PPM, each memory die can be structured, to be selected as the global management die or a local management die, with one or more controllers to interface with the multiple memory die packages and to handle current budget limits.

Abstract: A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

Abstract: Disclosed is a 3D architecture of ternary content-addressable memory (TCAM), comprising a first transistor layer, a second transistor layer, a third transistor layer and a fourth transistor layer. The first transistor layer and the second transistor layer are disposed on a first plane. The third transistor layer and the fourth transistor layer are respectively stacked on the first transistor layer and the second transistor layer in a second direction perpendicular to the first plane. Two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first memory cell of the TCAM. The other two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second memory cell of the TCAM.

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

Abstract: In an embodiment, an apparatus includes: a susceptor including substrate pockets; a gas injector disposed over the susceptor, the gas injector having first process regions, the gas injector including a first gas mixing hub and first distribution valves connecting the first gas mixing hub to the first process regions; and a controller connected to the gas injector and the susceptor, the controller being configured to: connect a first precursor material and a carrier gas to the first gas mixing hub; mix the first precursor material and the carrier gas in the first gas mixing hub to produce a first precursor gas; rotate the susceptor to rotate a first substrate disposed in one of the substrate pockets; and while rotating the susceptor, control the first distribution valves to sequentially introduce the first precursor gas at each of the first process regions as the first substrate enters each first process region.

Abstract: An image analyzation method and an image analyzation device are disclosed. The method includes: obtaining a first image which presents at least a first object and a second object; analyzing the first image to detect a first central point between a first endpoint of the first object and a second endpoint of the second object; determining a target region based on the first central point as a center of the target region; capturing a second image located in the target region from the first image; and analyzing the second image to generate status information which reflects a gap status between the first object and the second object.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Abstract: The present disclosure relates to a voltage regulating circuit, including an impedance circuit, a control unit and a power supply circuit. The impedance circuit has a first node and a second node, wherein the second node is electrically coupled to a load. The control unit is electrically coupled to the first node and configured to control a first voltage value of the first node according to a control signal. An input terminal of the power supply circuit is electrically coupled to the second node. An output of the power supply circuit is electrically coupled to the load. The power supply circuit is configured d to output a control voltage to the load according to a second voltage value of the second node.

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

Abstract: A method includes forming a body region of a first conductivity type and a doped region of a second conductivity type in a semiconductor substrate; forming a gate structure the substrate, and first gate spacers respectively on first and second sides of the gate structure; depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers respectively on the first and second sides of the gate structure; removing a first one of the third gate spacers from the first side of the gate structure, while leaving a second one of the third gate spacers on the second side of the gate structure; and patterning the second spacer layer into a second gate spacer by using the second one of the third gate spacers as an etching mask.

Abstract: A color filter module is provided. The color filter module is arranged on a display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes multiple sub-pixel regions arranged in an array. The color resist layer is arranged on the transparent substrate. The color resist layer includes multiple color resist units. The color resist units are respectively arranged across at least two sub-pixel regions, and the color resist units form a staggered array on the transparent substrate.

Abstract: A color filter module is provided. The color filter module is disposed on an electrophoretic display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes a plurality of pixel regions arranged in an array. Each of the plurality of pixel regions includes a plurality of sub-pixel regions. The color resist layer is disposed on the transparent substrate. Among the plurality of sub-pixel regions of the transparent substrate, a first sub-pixel region and a second sub-pixel region that correspond to a same color and are adjacent to each other are provided with a plurality of color resist units of the same color of the color resist layer. The plurality of color resist units are arranged in an array and arranged in a discontinuous pattern.

Abstract: A single-beam three-degree-of-freedom homodyne laser interferometer based on an array detector. A single-frequency laser beam is input to a Michelson interference structure, the measurement beam and the reference beam perform non-coaxial interference and form a single-beam homodyne interference signal by setting the angle of a reference plane mirror, the array detector is selected to effectively receive the single-beam homodyne interference signal, and finally, three-degree-of-freedom signal linear decoupling on the single-beam homodyne interference signal is achieved through a three-degree-of-freedom decoupling method based on Lissajous ellipse fitting.

Abstract: Provided are a latch mechanism and an electronic device case. The latch mechanism includes a base assembly, a pressing assembly and a first elastic member. The base assembly has an accommodating cavity, and a wall surface of the base assembly has a first through hole and a second through hole which are respectively communicated with the accommodating cavity. The pressing assembly includes a main body part, a button part and a bolt part, the main body part is disposed in the accommodating cavity, and the button part and the bolt part are respectively disposed on the main body part. The first elastic member is located in the accommodating cavity, one end of the first elastic member abuts against an inner wall of the accommodating cavity and the other end abuts against the main body part.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.