Patents by Inventor Ling Lu

Ling Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170316804
    Abstract: An apparatus and method provide for performing, using a heat-assisted magnetic recording head, multiple sequential writes to a recording medium, and recording a metric of write performance for each of the writes. The apparatus and method further provide for calculating fluctuations in the metric, detecting whether the head has a laser mode hopping problem using the metric fluctuations, and categorizing a severity of the laser mode hopping problem.
    Type: Application
    Filed: January 24, 2017
    Publication date: November 2, 2017
    Inventors: Minjie Ma, Tim Rausch, Edward Charles Gage, Pu-Ling Lu
  • Patent number: 9792949
    Abstract: An apparatus and method provide for performing, using a heat-assisted magnetic recording head, multiple sequential writes to a recording medium, and recording a metric of write performance for each of the writes. The apparatus and method further provide for calculating fluctuations in the metric, detecting whether the head has a laser mode hopping problem using the metric fluctuations, and categorizing a severity of the laser mode hopping problem.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: October 17, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Minjie Ma, Tim Rausch, Edward Charles Gage, Pu-Ling Lu
  • Patent number: 9786510
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: October 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Patent number: 9780218
    Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Hsu Liu, Jhen-cyuan Li, Chih-Chung Chen, Man-Ling Lu, Chung-Min Tsai, Yi-wei Chen
  • Patent number: 9691901
    Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Chia-Jong Liu, Chung-Fu Chang, Yen-Liang Wu, Man-Ling Lu, I-Fan Chang, Yi-Wei Chen
  • Patent number: 9646208
    Abstract: A method for computerized grouping contacts, an electronic device using the same and a computer program product are provided. The method for computerized grouping the contacts includes the following steps. At least one image is provided. Contacts are determined in the image. An interpersonal relation information is updated according to the image and the determined contacts. A contact group is suggested according to the interpersonal relation information.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: May 9, 2017
    Assignee: HTC CORPORATION
    Inventors: Jui-Lin Wu, Tai-Ling Lu
  • Patent number: 9634125
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 25, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Publication number: 20170098708
    Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Wen-Jiun Shen, Chia-Jong Liu, Chung-Fu Chang, Yen-Liang Wu, Man-Ling Lu, I-Fan Chang, Yi-Wei Chen
  • Patent number: 9595288
    Abstract: A method comprises performing a write operation using a heat-assisted magnetic recording (HAMR) drive operating at a plurality of temperatures. The method involves measuring a metric of write performance subsequent to the write operation at each of the operating temperatures. The method also involves detecting one or more laser mode hops using the metrics, and determining a temperature at which each of the detected mode hops occurred. The method further involves storing the temperature for each detected mode hop in a non-volatile memory of the drive. The method may involve mitigating laser mode hopping, such as by the drive avoiding the stored temperature(s).
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 14, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Alfredo Sam Chu, Pu-Ling Lu, Franklin P. Martens, John W. Dykes
  • Patent number: 9583135
    Abstract: An apparatus and method provide for performing, using a heat-assisted magnetic recording head, multiple sequential writes to a recording medium, and recording a metric of write performance for each of the writes. The apparatus and method further provide for calculating fluctuations in the metric, detecting whether the head has a laser mode hopping problem using the metric fluctuations, and categorizing a severity of the laser mode hopping problem.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 28, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Minjie Ma, Tim Rausch, Edward Charles Gage, Pu-Ling Lu
  • Patent number: 9529452
    Abstract: A touch input device includes a touch end, a sensing module, and a receiving module. The sensing module includes a sensing unit and a signal operation unit. The sensing unit detects a relative angle between the touch end and a display touch surface to generate a motion signal. The signal operation unit is coupled with the sensing unit and generates a result signal according to the motion signal. The receiving module includes a receiving end and a demodulator unit. The receiving end receives the result signal; the demodulator is coupled with the receiving end, wherein the receiving end transmits the result signal to the demodulator unit, and the demodulator unit generates a function signal according to the result signal.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 27, 2016
    Assignee: Raydium Semiconductor Corporation
    Inventors: Te-Chang Lin, Chien-Kuo Wang, Chia-Hsiu Lin, Ya-Ling Lu, Yi-Ming Chen, Wei-Yuan Cheng, Yu-Sheng Yeh
  • Patent number: 9515552
    Abstract: A voltage regulator with an on/off control on the control terminal of the power transistor of the voltage regulator. The power transistor of the voltage regulator drives the conversion from a first voltage to a second voltage. The voltage regulator provides a power-saving switch at the control terminal of the power transistor, and includes a power-saving control circuit controlling the power-saving switch. When the power-saving switch is turned on, the control signal for the power transistor is conveyed into the control terminal of the power transistor. When the power-saving switch is turned off, the connection between the control signal for the power transistor and the control terminal of the power transistor broken.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: December 6, 2016
    Assignee: Nuvoton Technology Corporation
    Inventors: Ming-Che Hung, Ciao-Ling Lu
  • Publication number: 20160267680
    Abstract: Methods and systems for determining frames and photo composition within multiple frames are provided. First, a plurality of frames, which are respectively captured with a predefined time interval are obtained. At least one object within at least two of the frames is detected. In some embodiments, a moving speed of the object is calculated according to the positions of the object in the respective frames and the predefined time interval, and candidate frames are selected from the frames according to the moving speed of the object in some embodiments, an overlapped area corresponding to the object within a first frame and a second frame is calculated, and at least one candidate frame is selected according to the overlapped area corresponding to the object. The at least one candidate frame is composed to generate a composed photo.
    Type: Application
    Filed: May 20, 2016
    Publication date: September 15, 2016
    Inventors: Bing-Sheng LIN, Yi-Chi LIN, Tai-Ling LU
  • Publication number: 20160260820
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: JHEN-CYUAN LI, SHUI-YEN LU, MAN-LING LU, YU-CHENG TUNG, CHUNG-FU CHANG
  • Patent number: 9425000
    Abstract: An embodiment provides a manufacturing method for a porous carbon material including: preparing a first solution including a surfactant, a carbon source material and a solvent; pouring the first solution into a silica sol aqueous solution to form a second solution; preparing a silicate aqueous solution; pouring the silicate aqueous solution into the second solution to form a third solution and to precipitate out an intermediate, wherein the intermediate includes the surfactant, the carbon source material and a silica template; performing a heating process on the intermediate to carbonize the intermediate; and removing the silica template of the carbonized intermediate to form a porous carbon material. Another embodiment of the disclosure provides a porous carbon material. The other embodiment provides a supercapacitor.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: August 23, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Ming Lin, Tsung-Yi Chen, Hong-Ping Lin, Wen-Ling Lu, Ssu-Jung Pan
  • Patent number: 9395825
    Abstract: A touch input device includes a body and a sensing module. The body has an external surface which encloses an accommodation space. The sensing module is disposed in the accommodation space and includes a sensing unit and a signal operation unit. The sensing unit generates a sensing signal. The signal operation unit generates a surface result signal according to the sensing signal to adjust a surface character of the external surface.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: July 19, 2016
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chia-Hsiu Lin, Te-Chang Lin, Ya-Ling Lu, Yi-Ming Chen, Wei-Yuan Cheng
  • Patent number: 9397190
    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.
    Type: Grant
    Filed: July 27, 2014
    Date of Patent: July 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Man-Ling Lu, Chia-Jong Liu, Wen-Jiun Shen, Yi-Wei Chen
  • Patent number: 9390738
    Abstract: Bits are written to a track of a heat-assisted magnetic recording medium via a write transducer at a first skew angle. The track is read via a read transducer oriented at a second skew angle different from the first skew angle. The second skew angle causes the read transducer be more closely aligned with boundaries of the bits than if oriented at the first skew angle.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 12, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Riyan Mendonsa, Douglas A. Saunders, Pu-Ling Lu, James H. McGlennen
  • Patent number: 9385191
    Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Patent number: 9373718
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Jhen-Cyuan Li, Shui-Yen Lu, Man-Ling Lu, Yu-Cheng Tung, Chung-Fu Chang