Abstract: A security module for use with a terminal comprises a data interface adapted to be coupled to a terminal, for receiving at least part of an algorithm code or the complete algorithm code from the terminal, and a power interface for receiving supply power. A volatile memory coupled to the power interface in order to have power supplied thereto stores the part of the algorithm code or the complete algorithm code received via the data interface. A processor performs, the algorithm code in order to obtain an algorithm code result that can be delivered to the terminal. Due to storing at least part of an algorithm code in the volatile memory of the security module, the algorithm code of the security module is effectively protected against being detected by spying from a potential attacker.

Abstract: A compiler system including a compiler configured to compile a source code into a machine language code is presented, so that the machine language code is executable on a processing unit, wherein the processing unit comprises an internal register that is changing its state responsive to an execution of the machine language code. The compiler is configured to encrypt the machine language code based on an encryption function that depends on the state of the internal register.

Abstract: A security device including a first external interface; a second external interface; and a security controller connected to said first external interface and said second external interface, said security controller being adapted to validate an access right based on a codeword received via said first interface to perform an encrypted memory access via said second external interface to an external memory coupleable to said second external interface, and to prevent that encrypted memory access via said first external interface or prevent any output of data via said first external interface depending on data received via said second external interface in case of a negative validation.

Abstract: A method and apparatus of recognizing an alarm scenario in a chip card. The method includes detecting a deviation of a property, and determining whether the deviation is a result of an alarm scenario.

Abstract: A integrated circuit comprises a circuit part to be protected and protective lines located at least one wiring level of the integrated circuit. In addition, the integrated circuit comprises logical gates coupled to the protective lines, whereby a logic circuit is formed, and a processing unit implemented to detect a manipulation of the integrated circuit by applying test patterns to the logic circuit and verifying a logic output value of the logic circuit responsive to the test patterns.

Abstract: In various embodiments, a method for biometric verification of a person is provided. The method may include detecting a biometric sample of a biometric characteristic of the person, and reading out a stored biometric feature from a data carrier and carrying out a comparison of the stored biometric feature with the detected biometric sample by means of a control unit; wherein at least one data area of the stored biometric feature is altered by means of disturbances, the control unit determines the altered disturbed data area of the stored biometric feature and omits the determined disturbed data areas during the comparison.

Abstract: A contactless chip module including a power supply, adapted to supply the contactless chip module with power obtained from an electromagnetic field; a first receiver adapted to receive an actively modulated signal; and a second receiver adapted to receive a passively modulated signal contained in the electromagnetic field.

Abstract: An apparatus including a sensor configured to sense a physical quantity, an actuator configured to manipulate the physical quantity in a predefined manner, and a detection circuit configured to output an alarm signal in case the sensor does not react to the manipulation of the physical quantity in an expected way.

Abstract: A method for operating a volatile random access memory as a detector, with predetermined information being stored in at least one area of the volatile random access memory. The method includes interrupting a supply voltage for the at least one area of the random access memory during a time period, reading information from the at least one area of the random access memory, and checking the extent to which the predetermined information and the information that has been read match or whether the predetermined information and the information which has been read have a predetermined relationship.

Abstract: An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at least one circuit part via testing lines. The testing unit is designed to start the functional self test when a starting signal for the functional self test is applied to the input, to evaluate test results that are present to determine whether they have a predefined relationship with predefined values, and to output data indicating the test result at the output. The testing unit is also designed to start the functional self test by internal circuit means and to evaluate the test results present.

Abstract: Microprocessor arrangement and a method for operating a microprocessor arrangement, where the microprocessor arrangement has an execution unit for controlling a program cycle and for processing arithmetic and logic operations, a working register which stores a result of an operation and which is coupled to a control element in the execution unit, a flag register which indicates information about the result of the operation using flag bits, and combinational logic elements which are connected to the working register, wherein the combinational logic elements are controlled such that the state of the flag bits in the flag register is updated after the executed operation only if execution of one of subsequent operations within the program cycle requires a status of the flag bits.

Abstract: A processor comprises a computation unit for performing an operation at a speed and a state unit, which has a state which changes in response to execution of an operation by the computation unit, the speed of the computation unit being controlled according to the state of the state unit. The state unit can e.g. be a capacitor or a unit with a thermal capacitance and controlling the speed of the computation unit can e.g. be effected via the frequency of a clock rate. In cryptographic applications the state unit is preferably so designed that the speed decreases when an operation is executed.

Abstract: In a module with a controller for a chip card, the controller having first and second I/O pads for data input and output, and the module having one I/O pad. Both of the first and second I/O pads of the controller are connected to only the one I/O pad of the module. In this manner, data output via one of the first and second I/O pads of the controller may be read and monitored by the controller via the other of the first and second I/O pads of the controller.

Abstract: In a system, there is communication between an electric circuit and a terminal within a scope of a terminal session, wherein the electric circuit has a current consumer for causing additional current consumption, and the terminal has a current consumption meter detecting the current consumption of the electric circuit and coupled to a checker checking authenticity of the electric circuit if the current consumption of the electric circuit has additional current consumption.

Abstract: Apparatus and method for generating an initial value for a pseudo-random number generator, with an oscillator configured to generate an oscillator signal; and a generator configured to generate the initial value based on the oscillator signal at least during part of a transient of the oscillator.

Abstract: An integrated circuit arrangement having a test line, a test signal generator which is coupled to the test line and is designed to pass a test signal onto the test line, and a comparison unit inclduing an input for applying a clock signal, the comparison unit being coupled to the test line and being designed to detect a propagation time of the test signal over the test line and to check whether the clock signal and the propagation time are in a predefined relationship.

Abstract: Method and device for creating a starting value for a pseudorandom number generator, having a reader configured to unstably read out an output value from a memory cell and a determiner configured to determine the starting value on the basis of the output value of the memory cell.

Abstract: A method for operating a volatile random access memory as a detector, with predetermined information being stored in at least one area of the volatile random access memory. The method includes interrupting a supply voltage for the at least one area of the random access memory during a time period, reading information from the at least one area of the random access memory, and checking the extent to which the predetermined information and the information that has been read match or whether the predetermined information and the information which has been read have a predetermined relationship.

Abstract: A data storing apparatus that wirelessly transmits data, wherein the apparatus is deformable so as to block wireless transmission of data when the apparatus is in the deformed state.

Abstract: An apparatus for checking an error detection functionality of a data processing circuit, comprising an arithmetic logic unit, which provides an output datum based on an input datum, and an error detection circuit that executes the error detection functionality and detects an error based on the output datum during correct execution of the error detection functionality, and generates an error signal, if an error is present, which comprises a control circuit that passes the error signal through to an error signal output in a normal operating mode, and blocks the error signal in a checking mode, does not let the error signal pass to the error signal output, influences the arithmetic logic unit, the error detection circuit or the input datum such that the error detection circuit detects an error during correct execution of the error detection functionality, and, if no error signal is received in response to influencing, outputs an alarm signal indicating an incorrect execution of the error detection functionality.