Abstract: During the creation of wiring plans for logic modules, the regions which are left free of interconnects by synthesis methods in upper metal planes are filled to a maximum degree with further interconnects. These interconnects serve to protect the integrated circuit. These further interconnects, depending on the availability of components for driving or evaluation, are embodied as sensor interconnects or else as connectionless interconnects only to confuse potential hackers.

Abstract: A processor comprises a first calculating unit, a second calculating unit and a control means for controlling the two calculating units, such that they selectively operate in a high security mode of operation processing complementary data or in a parallel mode of operation processing independent data, or in a security mode of operation processing the same data, or that they are in a power-saving mode of operation, wherein one of the calculating units is switched off.

Abstract: A carrier arrangement having a carrier configured to fix a semiconductor chip, contacts located on the carrier and configured to make contact with the semiconductor chip, and an overvoltage protection in a form of a spark gap arrangement formed between the contacts.

Abstract: An apparatus for checking an error recognition functionality of a memory circuit, wherein the memory circuit includes a memory circuit that stores a datum and a check value circuit that executes the error recognition functionality and a monitoring circuit, wherein the memory circuit provides the datum to the check value circuit, wherein the check value circuit checks the datum provided thereto for errors and outputs an error signal if an error is present, wherein the monitoring circuit is coupled to the check value circuit and influences the check value circuit, the memory circuit or the datum provided to the check value circuit so that the check value circuit would discover an error in a check in a case of correct execution of the error recognition functionality, and outputs an alarm signal if the check value circuit does not output an error signal upon the influence of the monitoring circuit.

Abstract: A chip card module including a substrate with a first side and an opposite second side. Contact areas are arranged on the first side, and a first conductor structure is arranged on the second side, the first conductor structure runs from one contact region to one of a another contact region and a second conductor structure, which is connected to the contact areas by means of a through connection in the substrate, so that the first conductor structure runs at least partly in a central region. The chip card module also includes a chip with connections which are arranged over the central region on the second side of the substrate, one of the connections being connected to the one contact region.

Abstract: Some embodiments of a chip module comprise a substrate, a semiconductor chip on the substrate, and a first layer between the substrate and the semiconductor chip, the first layer having high reflectivity for electromagnetic waves. Methods of protecting a chip module from electromagnetic radiation by interposing a protective layer between the chip and the substrate are also disclosed.

Abstract: An apparatus for detecting an attack on an electric circuit, wherein the electric circuit includes a current consumption threshold value discriminator to determine whether current consumption of the electric circuit exceeds a predetermined threshold value or not, and to generate a binary current limitation signal depending therefrom. The apparatus includes a monitor for monitoring the binary current limitation signal over a predetermined time interval, in order to indicate a signal characterizing the current consumption of the electric circuit over the predetermined time interval, and a detector for detecting an attack on the electric circuit based on the monitoring signal.

Abstract: A data transfer device having a data input and a data output has a data transmitter for transmitting data at the data input to the data output. The data transfer device includes a counter for decrementing/incrementing a counter value for each data passing the data output. The data transfer device also includes a monitor for monitoring the counter value and for outputting an alarm signal if the predetermined condition is met.

Abstract: A circuit arrangement for initializing a random number generator includes a volatile random access memory and an access device for storing and reading information in the random access memory. The information is read out from at least one area of the random access memory as a starting value or read out and transformed into a starting value. Furthermore, the circuit arrangement includes a switching device which is coupled to the access device and decouples the random access memory for a period of time from a supply voltage or a refresh signal. The random number generator is coupled to the access device and generates a random number sequence based on the starting value provided by the access device.

Abstract: An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at least one circuit part via testing lines. The testing unit is designed to start the functional self test when a starting signal for the functional self test is applied to the input, to evaluate test results that are present to determine whether they have a predefined relationship with predefined values, and to output data indicating the test result at the output. The testing unit is also designed to start the functional self test by internal circuit means and to evaluate the test results present.

Abstract: An integrated circuit is formed on a non-planar substrate. The integrated circuit is formed over a plurality of layers. Chemical or physical changes in the microstructure of the substrate cause the bending of the substrate, in one or more propagation directions.

Abstract: An IC chip having a protective structure that is distributed over the semiconductor chip in such a manner that it is not possible to trigger a malfunction in the circuit by means of irradiation without the protective structure also being affected by the irradiation. To this end, redundant conductors are provided or connections having radiation-dependent conductivity or dielectric constant are provided or the test lines of a memory are arranged between the bit lines.

Abstract: Integrated circuit arrangement, in which bearing areas of mutually opposing sides of a carrier and of a substrate layer, which carries circuit structures, are bonded by means of an adhesive layer. The adhesive bond is produced from adhesives forming at least two adhesive tracks. The first adhesive track is formed in a region of an externally accessible seam between the substrate layer and the carrier, and the second adhesive track is formed parallel to the first adhesive track in an inner region of the bearing areas that face one another.

Abstract: Provision is made of a method and an apparatus for assessing one-time programmable cells, in which an electrical characteristic quantity of a cell is ascertained. This electrical characteristic quantity is compared with a first predetermined threshold value and a second predetermined threshold value, and a signal signaling an uncertain programming state is produced if the electrical characteristic quantity is between the first predetermined threshold value and the second predetermined threshold value.

Abstract: Integrated circuit arrangement, in which bearing areas of mutually opposing sides of a carrier and of a substrate layer, which carries circuit structures, are bonded by means of an adhesive layer. The adhesive bond is produced from adhesives forming at least two adhesive tracks. The first adhesive track is formed in a region of an externally accessible seam between the substrate layer and the carrier, and the second adhesive track is formed parallel to the first adhesive track in an inner region of the bearing areas that face one another.

Abstract: A shielding device includes optical and/or electrical shielding disposed on the side of the integrated circuit in the semiconductor chip facing the substrate. Preferred configurations use an SOI substrate with the integrated circuit in the body silicon layer and the insulator layer as a device for optical shielding from the bulk silicon layer. Electrical conductors may be present as an optical and electrical shielding device in the bulk silicon layer, and they may be connected to the circuit using vias.

Abstract: Microprocessor arrangement and a method for operating a microprocessor arrangement, where the microprocessor arrangement has an execution unit for controlling a program cycle and for processing arithmetic and logic operations, a working register which stores a result of an operation and which is coupled to a control element in the execution unit, a flag register which indicates information about the result of the operation using flag bits, and combinational logic elements which are connected to the working register, wherein the combinational logic elements are controlled such that the state of the flag bits in the flag register is updated after the executed operation only if execution of one of subsequent operations within the program cycle requires a status of the flag bits.

Abstract: An IC chip having a protective structure that is distributed over the semiconductor chip in such a manner that it is not possible to trigger a malfunction in the circuit by means of irradiation without the protective structure also being affected by the irradiation. To this end, redundant conductors are provided or connections having radiation-dependent conductivity or dielectric constant are provided or the test lines of a memory are arranged between the bit lines.

Abstract: Provision is made of a method and an apparatus for assessing one-time programmable cells, in which an electrical characteristic quantity of a cell is ascertained. This electrical characteristic quantity is compared with a first predetermined threshold value and a second predetermined threshold value, and a signal signaling an uncertain programming state is produced if the electrical characteristic quantity is between the first predetermined threshold value and the second predetermined threshold value.

Abstract: A processor comprises a first calculating unit, a second calculating unit and a control means for controlling the two calculating units, such that they selectively operate in a high security mode of operation processing complementary data or in a parallel mode of operation processing independent data, or in a security mode of operation processing the same data, or that they are in a power-saving mode of operation, wherein one of the calculating units is switched off.