Abstract: A semiconductor package provided herein includes a package substrate and a semiconductor device. The package substrate includes a redistribution structure, an interconnect structure bonded to the interconnect structure and an insulation material laterally surrounding the interconnect structure, wherein the redistribution structure has a reduced structure and the insulation material fills the reduced structure. The semiconductor device is bonded to the package substrate. In addition, a method of fabricating a semiconductor package is also provided and includes a precut process forming the reduced structure in the redistribution structure of the package substrate.

Abstract: Methods, systems and computer devices are provided for adjusting a frame-listening cycle. The method includes: configuring, by a server, a fixed frame-listening cycle of an electronic shelf label according to a time period; and sending, by the server, a second frame-listening cycle modification command through a base station when the server is to issue the fast response service during the low power consumption time period, so that the electronic shelf label modifies the current frame-listening cycle to a fast frame-listening cycle according to the second frame-listening cycle modification command. According to the present disclosure, the electronic shelf label can not only respond to the fast response service in real time, but also keep the low power consumption of a long frame-listening cycle, thereby simultaneously satisfying the requirements of high real-time performance and low power consumption of the electronic shelf label.

Abstract: A dynamic frequency allocation method for base stations, a shelf label system and a computer device are provided. The method includes: obtaining a current connectivity structure of base stations; obtaining a current weight degree of each base station based on a frequency interval weight between base stations in the current connectivity structure; performing priority classification on all current base stations to obtain a current priority type of each base station; and obtaining a current allocated frequency of each base station based on the current priority type of the base station, the current weight degree of the base station, the frequency interval weight and a current available frequency set.

Abstract: Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.

Abstract: A method for inhibiting immune responses, comprising administering to a subject in need thereof an effective amount of a pharmaceutical composition comprising salvigenin, and optionally cirsimaritin, rosmarinic acid, carvacrol, or a combination thereof.

Abstract: A method for manufacturing a flash memory device is provided. The method includes forming a plurality of isolation structures in a substrate, an opening is formed between two adjacent isolation structures, and conformally depositing a first silicon seed layer on the substrate and the isolation structures and performing a first cycle. The first cycle includes performing a first deposition process to conformally form a first amorphous silicon layer on the first silicon seed layer. A first recess is defined by the first amorphous silicon layer. A first in-situ chlorine etching process is performed to widen the caliber of the first recess. The method includes performing a first thermal annealing process to transform the first amorphous silicon layer into a first polysilicon layer. The method includes performing an amorphous silicon deposition process to form an amorphous silicon layer on the first polysilicon layer and completely fill the opening.

Abstract: A shelf label system and a method thereof are provided. The shelf label system includes base stations and at least one server. The at least one server may be configured to: obtain a target network topological structure according to a master base station having a shallowest topological depth and a ranging result between a base station and a superior base station of the base station, where each base station has a single superior base station; generate a transceiving time slot periodic table by allocating a transceiving time slot to each base station according to the target network topological structure; and obtain a synchronous network of the shelf label system by instructing the base stations to transmit and receive synchronous signals according to the transceiving time slot periodic table. The shelf label system further includes electronic shelf labels that receive the synchronous signals from the base stations.

Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Abstract: The disclosure relates to a load cell including an elastic element, at least one strain gauge and a limitation element. The elastic element includes a first end portion, a second end portion and a deformation region. The first end portion and the second end portion are arranged along an axial direction and opposed to each other. The deformation region is located between the first end portion and the second end portion. The at least one strain gauge is disposed in the deformation region. When a force is exerted on the first end portion in a first direction, the deformation region is deformed to drive the at least one strain gauge to change shape, so that the force is measured and standardized under a specific range. The limitation element is connected to the elastic element. A gap is formed between the limitation element and the elastic element.

Abstract: A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.

Abstract: A dynamic frequency allocation method for base stations, a shelf label system and a computer device are provided. The method includes: obtaining a current connectivity structure of base stations; obtaining a current weight degree of each base station based on a frequency interval weight between base stations in the current connectivity structure; performing priority classification on all current base stations to obtain a current priority type of each base station; and obtaining a current allocated frequency of each base station based on the current priority type of the base station, the current weight degree of the base station, the frequency interval weight and a current available frequency set.

Abstract: A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.

Abstract: A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Abstract: A shelf label system and a method thereof are provided. The shelf label system includes base stations and at least one server. The at least one server may be configured to: obtain a target network topological structure according to a master base station having a shallowest topological depth and a ranging result between a base station and a superior base station of the base station, where each base station has a single superior base station; generate a transceiving time slot periodic table by allocating a transceiving time slot to each base station according to the target network topological structure; and obtain a synchronous network of the shelf label system by instructing the base stations to transmit and receive synchronous signals according to the transceiving time slot periodic table. The shelf label system further includes electronic shelf labels that receive the synchronous signals from the base stations.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

Abstract: An assembly including at least one semiconductor die and an interposer is provided. A packaging substrate including substrate bonding pads is provided. The packaging substrate includes a first horizontal surface facing the assembly, a second horizontal surface located on an opposite side of the first horizontal surface, and an opening extending between the first horizontal surface and the second horizontal surface. The assembly is attached to the packaging substrate by bonding first solder material portions bonded to a respective one of the substrate bonding pads and to a respective one of first interposer bonding pads located on the interposer.