Patents by Inventor Min Liang

Min Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11594479
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Pei-Rong Ni, Chia-Min Lin, Yu-Min Liang, Jiun-Yi Wu
  • Patent number: 11564029
    Abstract: The inventive subject matter is directed to headset audio systems having resonance chambers designed to improve a system's frequency response in certain ranges. Systems of the inventive subject matter include a casing that both holds a speaker driver and creates two resonance chambers. Each resonance chamber vents to ambient air outside the casing, where the length and cross-sectional areas of each vent can impact the system's frequency response. Each resonance chamber is tuned to a resonant frequency to improve the system's frequency response across a range of frequencies on either side of each chamber's resonant frequency.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 24, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kai Lin Shen, Sheng Hung Wang, Penhao Ma, Wei-Min Liang
  • Patent number: 11557444
    Abstract: Key switches of the inventive subject matter are designed to give users the tactile feel of key switches from expensive mechanical keyboards without drawback typically associated with alternative key switches. In some embodiments, key switches described in this application are designed to function with a sheet of membrane switches, while in other embodiments, key switches of the inventive subject matter incorporate optical switching in place of membrane switching. Embodiments for use with membrane switching feature a plunger and rocker combination that prevents the pressure from a user's key press from being directly transferred to a membrane switch, thereby reducing wear and tear. In optical switching embodiments, pressing the key switch causes an actuator, e.g., come between an optical emitter/receiver pair to register a key press.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: January 17, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jian-Cheng Lai, Wei-Min Liang, Kuo Shou Yu
  • Publication number: 20230009553
    Abstract: Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Yu-Min Liang, Jiun-Yi Wu, Chien-Hsun Lee
  • Publication number: 20220415776
    Abstract: A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Liang Chen, Kuan-Lin Ho, Pei-Rong Ni, Chia-Min Lin, Yu-Min Liang, Jiun-Yi Wu
  • Patent number: 11540216
    Abstract: This disclosure provides an interactive electronic tag device communication system and method, including: a background server, a base station, an electronic tag device and an external device; the external device transmits first data to an electronic tag device through a second communication path; the electronic tag device receives the first data and transmits the same to a base station through a first communication path, and enters a fast monitoring mode; the base station receives the first data and transmits the same to background server; the background server generates a control instruction and second data, and transmits the same to the base station; the base station receives a fast wake-up instruction, the control instruction and the second data and transmits the same to electronic tag device through first communication path; the electronic tag device receives fast wake-up instruction, control instruction and second data, and switches to the normal monitoring mode after completing communication.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 27, 2022
    Assignee: HANSHOW TECHNOLOGY CO., LTD.
    Inventors: Min Liang, Shiguo Hou, Jun Chen, Qi Jiang, Yang Zhao
  • Publication number: 20220406699
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Pei-Rong Ni, Chia-Min Lin, Yu-Min Liang, Jiun-Yi Wu
  • Patent number: 11528553
    Abstract: The inventive subject matter is directed to headset audio systems having resonance chambers designed to improve a system's frequency response in certain ranges. Systems of the inventive subject matter include a casing that both holds a speaker driver and creates two resonance chambers. Each resonance chamber vents to ambient air outside the casing, where the length and cross-sectional areas of each vent can impact the system's frequency response. Each resonance chamber is tuned to a resonant frequency to improve the system's frequency response across a range of frequencies on either side of each chamber's resonant frequency.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: December 13, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kai Lin Shen, Sheng Hung Wang, Penhao Ma, Wei-Min Liang
  • Publication number: 20220392832
    Abstract: A method of forming a semiconductor structure includes the following operations. A first conductive structure is formed on a first side of a first glass carrier. A second glass carrier is bonded to the first conductive structure. Conductive vias are formed to penetrate through the first glass carrier, and the conductive vias are electrically connected to the first conductive structure. A second conductive structure is formed on a second side of the first glass carrier opposite to the first side, and the second conductive structure is electrically connected to the conductive vias.
    Type: Application
    Filed: June 6, 2021
    Publication date: December 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Yu-Min Liang, Tsung-Ding Wang, Jiun-Yi Wu, Chien-Hsun Lee
  • Patent number: 11515173
    Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
  • Publication number: 20220374079
    Abstract: According to various embodiments, a display device may be provided. The display device may include: a receiver configured to receive user data based on an electroencephalography measurement; at least one light source; and a controller configured to control the at least one light source based on the user data.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 24, 2022
    Inventors: Min-Liang Tan, Kian Sin Yeo, Beng Leong Toh, Ji Fong Lim, Gui Mei Dai, Kah Yong Lee, Aninda Kanti Sen
  • Patent number: 11508640
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
  • Patent number: 11508477
    Abstract: A surgery system includes a contactless control panel, an infrared camera, a computer and a display. The contactless control panel includes control areas which are arranged in a predetermined pattern and are coated with infrared reflective material to reflect infrared radiation. The infrared camera captures an infrared image of the control areas. The computer performs image recognition on the infrared image, determines, based on the predetermined pattern stored in advance and a result of the image recognition, which one of the control areas is masked, and generates a device control signal based on a function corresponding to the one of the control areas that is determined to be masked. The display device displays images based on the device control signal.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Main Orthopaedic Biotechnology Co., Ltd.
    Inventor: Min-Liang Wang
  • Publication number: 20220367315
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
  • Publication number: 20220367414
    Abstract: A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar arid a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A first surface of the first die and a second surface of the second die are at substantially same level.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: CHI-YANG YU, KUAN-LIN HO, CHIN-LIANG CHEN, YU-MIN LIANG
  • Publication number: 20220359406
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20220352109
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.
    Type: Application
    Filed: August 29, 2021
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Nien-Fang Wu, Hai-Ming Chen, Yu-Min Liang, Jiun-Yi Wu
  • Publication number: 20220337931
    Abstract: Embodiments of the inventive subject matter described in this application are directed to headset audio systems that incorporate components designed to improve sound reproduction in certain ranges. For example, in some embodiments, an acoustic chamber and a venting portion are incorporated into an internal portion of a headset audio system such that the vent is configured to improve bass response. Different vent shapes and sizes can affect speaker performance. Moreover, in some embodiments, the acoustic chamber can additionally include a vent.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Wei-Min Liang, Wen Ning Chang
  • Patent number: 11463676
    Abstract: A stereoscopic visualization system using shape from shading algorithm is an image conversion device connected between a monoscopic endoscope and a 3D monitor. The system applies the algorithm which generates a depth map for a 2D image of video frames. The algorithm first calculates a direction of a light source for the 2D image. Based upon the information of light distribution and shading for the 2D image, the depth map is generated. The depth map is used to calculate another view of the original 2D image by depth image based rendering algorithm in generation of stereoscopic images. After the new view is rendered, the stereoscopic visualization system also needs to convert the display format of the stereoscopic images for different kinds of 3D displays. Based on this method, it can replace the whole monoscopic endoscope with a stereo-endoscope system and no modification is required for the monoscopic endoscope.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 4, 2022
    Assignee: MEDICALTEK CO. LTD.
    Inventors: Yen-Yu Wang, Kai-Che Liu, Atul Kumar, Min-Liang Wang
  • Publication number: 20220302064
    Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Wei-Yu CHEN, Chi-Yang YU, Kuan-Lin HO, Chin-Liang CHEN, Yu-Min LIANG, Jiun Yi WU