Patents by Inventor Min Liang

Min Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230308976
    Abstract: Disclosed are methods and devices for facilitating the seamless handover of Bluetooth communications of a Bluetooth accessory device from a first Bluetooth host to a second Bluetooth host. A first host identifier uniquely identifies the first Bluetooth host for its Bluetooth communications, and a second host identifier uniquely identifies the second Bluetooth host for its Bluetooth communications. The host identifiers are stored in the Bluetooth accessory device, and they are provided to an application on the mobile device that allows a user to select either the first or the second host as the selected host for the Bluetooth accessory device, without having to re-pair the host device to the accessory device. Because re-pairing is not necessary, the user can quickly and seamlessly switch the Bluetooth accessory's communications among multiple different host devices.
    Type: Application
    Filed: May 31, 2021
    Publication date: September 28, 2023
    Inventors: Chee Oei CHAN, Min-liang TAN
  • Publication number: 20230307305
    Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Jiun-Yi Wu, Hsin-Yu Pan, Tsung-Ding Wang, Yu-Min Liang, Wei-Yu Chen
  • Publication number: 20230307385
    Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
  • Publication number: 20230300590
    Abstract: A fail-safe on-board unit, a movable device, and a control method for a vehicle which will automatically and reliably broadcast a distress signal to a rescue center in the event of accident includes in the on-board unit a first subscriber identity module (SIM), a second SIM, a main processor, a modem, a radio frequency (RF) switch module, and an antenna module with several antennas. The main processor selects the first SIM and / or the second SIM to make a call to generate a baseband signal, and outputs the baseband signal to the modem, the modem converts the baseband signal into an RF signal, and outputs the RF signal to the RF switch module to transmit outward via one or more antennas of the antenna module. The on-board unit has a wider network coverage to ensure higher success rate of emergency calls.
    Type: Application
    Filed: February 6, 2023
    Publication date: September 21, 2023
    Inventors: FENG-YUAN LI, ZHI-CHENG YU, XIAO-MIN LIANG
  • Patent number: 11749594
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
  • Publication number: 20230270499
    Abstract: A method for designing a bone plate to be used in an orthopedic surgery and to be placed on a bone structure includes: constructing a three-dimensional (3D) model of the bone structure; controlling a display screen to display an image that corresponds with the 3D model; in response to a plurality of designated points inputted on the image, calculating a plurality of sets of 3D coordinates respectively for the plurality of designated points, and generating an extension route based on the plurality of sets of 3D coordinates; and generating a 3D model of the bone plate based on the extension route and at least one pre-stored bone plate template.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Inventor: Min-Liang WANG
  • Publication number: 20230274667
    Abstract: An electronic shelf label positioning system, an electronic shelf label and a guide rail. The electronic shelf label positioning system includes the electronic shelf label, the guide rail, a PDA and a background server. The electronic shelf label includes a main control SoC, a card reader IC, a screen and a power supply device. The main control SoC is configured to control the screen display and to communicate with an AP. The power supply device is configured to supply power to the electronic shelf label. The guide rail includes a guide rail identification area and a label area. The label area is installed with a plurality of wireless labels each having a unique non-repeated ID number. The guide rail identification area is installed with an identity recognition device, which includes a guide rail ID consisting of the ID numbers of the wireless labels sequentially arranged and summarized.
    Type: Application
    Filed: May 9, 2023
    Publication date: August 31, 2023
    Inventors: Shiguo HOU, Jianguo ZHAO, Min LIANG, Le ZHUO, Sheng YI, Yang ZHAO, Yanwei WANG, Linjiang WANG
  • Publication number: 20230260945
    Abstract: A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Yu-Min Liang, Jung-Wei Cheng
  • Patent number: 11727015
    Abstract: Systems and methods of monitoring for anomalous data records. The system conducts a method including: receiving a data record associated with at least one meta attribute to determine whether subsequent processing of the data record is warranted; generating an anomaly prediction for the data record based on a detection model and the at least one meta attribute associated with the data record, the detection model defined by a plurality of score distribution representations based on quantile bins and a dynamic quantile weight for providing an interim anomaly measure corresponding to respective score distribution representations, wherein the anomaly prediction is generated based on a combination of interim anomaly measures associated with respective meta attributes associated with the data record; and transmitting a signal representing the anomaly prediction for presentation at a user device for identifying one or more data records for subsequent data processes.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 15, 2023
    Inventors: Kanika Vij, Igor Reshynsky, Hameet Jassal, Emma Hu, Min Liang, Adam Lazure, Esther Choi, Rowan Comish, Jingyi Gao, Gladys Leung, Diane Fenton
  • Patent number: 11705378
    Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Jiun-Yi Wu, Hsin-Yu Pan, Tsung-Ding Wang, Yu-Min Liang, Wei-Yu Chen
  • Patent number: 11705408
    Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
  • Patent number: 11698309
    Abstract: The disclosure relates to a linear actuator including a base, a linear motor, a load cell and a rotary motor. The linear motor is disposed on the base and includes a fixed coil module and a movable magnetic backplane. The fixed coil module is fixed on the base, and the movable magnetic backplane is configured to slide relative to the fixed coil module along a first direction. The rotary motor is rotated around a central axis in parallel with the first direction. The load cell has two opposite sides parallel to the first direction, respectively. The movable magnetic backplane of the linear motor and the rotary motor are connected to the two opposite sides of the load cell, respectively. The load cell is subjected to a force applied thereto by the rotary motor and parallel to the first direction, and configured to convert the force into an electrical signal.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 11, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Han Hsu, Zi-Xuan Huang, Yu-Xian Huang, Yi-Min Liang, You-Chyau Tsai, Tsung-En Chan, Hong-Chih Chen
  • Patent number: 11688693
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20230178466
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 8, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Pei-Rong Ni, Chia-Min Lin, Yu-Min Liang, Jiun-Yi Wu
  • Publication number: 20230126207
    Abstract: A surgical navigation system includes a first tracking unit, a second tracking unit and a processing unit. The first tracking unit captures a first infrared image of a position identification unit that includes a reference target fixed on a patient and an instrument target disposed on a surgical instrument. The second tracking unit captures a second infrared image of the position identification unit. The processing unit performs image recognition on the first and second infrared images with respect to the position identification unit, and uses, based on a result of the image recognition, a pathological image and one of the first and second infrared images to generate an augmented reality image. When both the first and second images have both the reference target and the instrument target, one of the first image and the second image with a higher accuracy is used to generate the augmented reality image.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 27, 2023
    Inventor: Min-Liang WANG
  • Patent number: 11616037
    Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: March 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
  • Publication number: 20230091737
    Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Inventors: Chien-Hsun Chen, Yu-Min Liang, Yen-Ping Wang, Jiun Yi Wu, Chen-Hua Yu, Kai-Chiang Wu
  • Publication number: 20230091904
    Abstract: A sensing system is provided that includes a first sub-sensing system having a first azimuth plane. The first sub-sensing system includes a Gradient-index lens, and a first plurality of antenna elements arranged adjacent to the Gradient-index lens and configured to receive a first signal emanating from a first field of view. The sensing system also includes a second sub-sensing system having a second azimuth plane oriented at an angle with respect to the first azimuth plane and a second plurality of antenna elements configured to receive a second signal emanating from a second field of view.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 23, 2023
    Applicant: Lunewave Inc.
    Inventors: Hao Xin, Jiang Xin, Min Liang, Ning Cao
  • Patent number: 11610601
    Abstract: A method and apparatus for determining a speech presence probability and an electronic device are provided. According to present disclosure, a metric parameter of a signal to noise ratio of a signal of a first channel and a metric parameter of a signal power level difference between the first channel and the second channel are introduced in determining the speech presence probability, the normalization and non-linear transformation processing is performed on the above-mentioned metric parameters, and the speech presence probability is obtained by fitting the product term and a first power term of a power exponent of the above-mentioned parameters. Therefore, the calculation amount of calculating the speech presence probability is reduced, the calculation result has good robustness to parameter fluctuations, and the disclosure can be widely applied to various application scenarios of dual-microphone speech enhancement systems.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 21, 2023
    Assignee: CHINA ACADEMY OF TELECOMMUNICATIONS TECHNOLOGY
    Inventors: Fabing Wang, Min Liang
  • Patent number: D982567
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: April 4, 2023
    Assignee: Nanning FuLian FuGui Precision Industrial Co., Ltd.
    Inventors: Xiao-Min Liang, Zhi-Cheng Yu