Patents by Inventor Ming Huang

Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12001079
    Abstract: An optical camera lens including a first lens, a second lens, and a third lens arranged in sequence from the object side to the image side. The first lens has a positive refractive power, and includes a first object side surface and a first image side surface opposite to the first object side surface. The second lens has a negative refractive power, and includes a second object side surface and a second image side surface opposite to the second object side surface, wherein the second image side surface is concave. The third lens has a positive refractive power, and includes a third object side surface and a third image side surface opposite to the third object side surface, wherein both the third object side surface and the third image side surface are convex. The optical camera lens satisfies the following condition: 2<(f+BFL)/OD1<7.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 4, 2024
    Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventors: Ming-Huang Tseng, Guo-Yang Wu, Hsi-Ling Chang
  • Patent number: 12002684
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Patent number: 12003399
    Abstract: Embodiments of this application provide a probe request and response technology between a station and a plurality of AP MLDs. If the station wants to obtain a communication parameter of a nontransmitted BSSID AP, the station may send a probe request frame to a nontransmitted BSSID AP in an MBSSID set, and a transmitted BSSID AP in the MBSSID set may reply with a probe response frame. Alternatively, if the station wants to probe a plurality of AP MLDs at a time, the station may send the probe request frame to one transmitted BSSID AP in the MBSSID set, to request the AP to reply with a communication parameter of the nontransmitted BSSID AP. The nontransmitted BSSID AP and the transmitted BSSID AP may belong to different AP MLDs.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: June 4, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuchen Guo, Ming Gan, Yunbo Li, Guogang Huang
  • Patent number: 11998894
    Abstract: A composite solid base catalyst, a manufacturing method thereof and a manufacturing method of glycidol are provided. The composite solid base catalyst includes an aluminum carrier and a plurality of calcium particles. The plurality of calcium particles are supported by the aluminum carrier. Beta basic sites of the composite solid base catalyst are 0.58 mmol/g-3.89 mmol/g.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: June 4, 2024
    Assignees: NATIONAL TSING HUA UNIVERSITY, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., LTD., DAIREN CHEMICAL CORP.
    Inventors: De-Hao Tsai, Yung-Tin Pan, Che-Ming Yang, Ching-Yuan Chang, Ding-Huei Tsai, Chien-Fu Huang, Yi-Ta Tsai
  • Patent number: 12002186
    Abstract: Methods and systems to detect and blend a surround area to avoid filtering artifact due to the area in image filtering are disclosed. The described methods include a compensation step and can be applied to arbitrary images with padded areas of arbitrary shape, such as letterboxes, pillar-boxes, ovals, or other shapes, including logos and close captions. Such methods detect the surround areas in the image with possible compression artifact and noise, and then perform blending to minimize the effects of the surround areas for any arbitrary image filtering operations.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: June 4, 2024
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Tsung-Wei Huang, Guan-Ming Su
  • Publication number: 20240174561
    Abstract: Various aspects of the present disclosure relate to a method of cleaning a glass substrate. The method includes contacting the glass substrate with a cleaning agent for a predetermined amount of time. The cleaning agent includes a substance having a sublimation point in a range of from about ?90° C. to about ?70° C. and the cleaning agent is dispersed in a gas carrier.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 30, 2024
    Inventors: Robert Randall Hancock, JR., En Hong, Ming-Huang Huang, Aize Li
  • Publication number: 20240175104
    Abstract: A method of preparing scandium metal includes mixing aluminum powder and scandium fluoride powder to form a mixture, heating the mixture in a vacuum environment to react the aluminum powder with the scandium fluoride powder for forming aluminum fluoride gas and scandium metal, and removing the aluminum fluoride gas by evacuation to obtain the scandium metal.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Chun FU, Yang-Sheng HUANG, Chia-Ming CHANG
  • Publication number: 20240178319
    Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
  • Publication number: 20240178090
    Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin
  • Publication number: 20240177657
    Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a driving transistor; a storage capacitor; a first reset transistor having a gate electrode connected to a first gate line in a present stage of a plurality of first gate lines, a source electrode connected to a respective first reset signal line of a plurality of first reset signal lines, and a drain electrode connected to an anode of a light emitting element; and a second reset transistor having a gate electrode connected to a first gate line in a previous stage of the plurality of first gate lines, a source electrode connected to a respective second reset signal line of a plurality of second reset signal lines, and a drain electrode connected to a drain electrode of the driving transistor.
    Type: Application
    Filed: September 17, 2021
    Publication date: May 30, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Rui Wang, Chao Zeng, Ming Hu, Haijun Qiu, Weiyun Huang, Tianyi Cheng
  • Publication number: 20240179065
    Abstract: An auto-configuration method for a time-sensitive networking (TSN) system includes obtaining, by a first OPC UA client module, a TSN configuration of a stream; transmitting, by the first OPC UA client module, the TSN configuration to an OPC UA server module of a centralized user configuration (CUC) in the TSN system; obtaining, by the CUC, a routing information and scheduling of the stream according to the TSN configuration and a network topology; sending, by the first OPC UA client module, a request to the OPC UA server to obtain the routing information and scheduling of the stream; and configuring the routing information and scheduling of the stream to a plurality of end stations in the TSN system after the plurality of end stations are online.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 30, 2024
    Applicant: Moxa Inc.
    Inventors: Yueh-Ming Ko, Chun-Yu Lin, Tzu-Lun Huang
  • Publication number: 20240178132
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a second insulating layer formed over the first insulating layer, and a conductive structure formed within the second insulating layer. The conductive structure includes a metal line having a plane top surface, a bottom surface having a first concave recess portion and a plane portion, and a sidewall adjoining the plane top surface and the plane portion of the bottom surface. The conductive structure also includes a first metal feature formed within the first concave recess. The semiconductor device structure further includes a second metal feature formed below the first insulating layer and electrically connected to the first metal feature.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Zhen YU, Lin-Yu HUANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240178120
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.
    Type: Application
    Filed: February 8, 2023
    Publication date: May 30, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Tzu-Sung Huang, Wei-Kang Hsieh, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Chu-Chun Chueh
  • Publication number: 20240178069
    Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 30, 2024
    Inventors: Lin-Yu HUANG, Sheng-Tsung WANG, Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240176059
    Abstract: A light guide plate structure includes a body and a plurality of microstructures. The body includes a first surface, a second surface, and a light incident surface. The light incident surface is connected to the first surface and the second surface. The light incident surface faces a light source, and light incident by the light source via the light incident surface has a light source direction on the body. The microstructures are formed on the first surface and have crests and troughs along a second direction, where projections of the crests on the first surface are distributed on a plurality of first wave trajectories, each of the first wave trajectories extends along the light source direction, and the troughs have ups and downs in the first direction. The light guide plate structure may improve the optical grade of pictures of a display device. A backlight module is also provided.
    Type: Application
    Filed: August 4, 2023
    Publication date: May 30, 2024
    Inventors: CHIEN-MING CHU, YA-FANG HUANG, HUA-YING CHUANG
  • Patent number: 11992322
    Abstract: A heart rhythm detection method and system by using radar sensor is capable of collecting an original signal using a radar sensor toward at least one subject, and converting the original signal to a two dimensional image information (i.e., spectrogram) using the concept of image vision. Then, the neural network automatically learns which heartbeat frequency should be focused on and which heartbeat frequency should be filtered out in the two dimensional image information through deep learning, so that the heartbeat frequencies can be extracted effectively.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 28, 2024
    Assignee: IONETWORKS INC.
    Inventors: Jing-Ming Guo, Ting Lin, Chia-Fen Chang, Jeffry Susanto, Yi-Hsiang Lin, Po-Cheng Huang, Yu-Wen Wei
  • Patent number: 11993747
    Abstract: The present disclosure relates to methods for treating a water zone of a subterranean formation by injecting a mixture including an anionic surfactant and an amine, followed by CO2, to reduce water production from the formation.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: May 28, 2024
    Assignee: Saudi Arabian Oil Company
    Inventors: Zuhair Al-Yousif, Abdulaziz S. Al-Qasim, Shaohua Chen, Tianping Huang, Ming Han
  • Patent number: 11995471
    Abstract: A resource integration method includes the following steps: a receiving module receives access information from a guest operating system on the host device; the access information is used to determine whether the frame rate is lower than a frame rate threshold; when the receiving module determines that the frame rate is lower than the frame rate threshold, the receiving module transmits an external resource request signal to the receiving module; after the receiving module receives the external resource request signal, a resource management module (which is located in the bridge module) selects an optimal external device from a specific category (among a plurality of categories in a candidate list), and a calculation operation or a storage operation corresponding to the specific category is transmitted to the optimal external device for calculation or storage by the bridge module.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 28, 2024
    Assignee: ACER INCORPORATED
    Inventors: Kuan-Ju Chen, Wen-Cheng Hsu, Hung-Ming Chang, Chih-Wen Huang, Chao-Kuang Yang
  • Patent number: 11996466
    Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
  • Publication number: 20240170613
    Abstract: An optoelectronic semiconductor element is provided. The optoelectronic semiconductor element includes a semiconductor stack and a first metal layer. The semiconductor stack includes a first portion and a second portion stacked in sequence, with the second portion including an active region. The first metal layer is located on the first portion and is electrically connected to the first portion. A top-view outline of the first portion shows a first pattern, a top-view outline of the second portion shows a second pattern, and a top-view outline of the first metal layer shows a third pattern. The area ratio of the third pattern to the first pattern is from 0.5% to 10%.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 23, 2024
    Inventors: Ching-En Huang, Chuang-Sheng Lin, Hao-Ming Ku, Shih-I Chen