Patents by Inventor Ming Huang
Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984379Abstract: Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.Type: GrantFiled: July 8, 2021Date of Patent: May 14, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
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Patent number: 11983363Abstract: A user gesture behavior simulation system includes a touch gesture recording and editing device and a touch gesture simulation device. When at least one touch gesture is implemented on a record touch object with at least one finger of a user, the at least one touch gesture is recorded by the touch gesture recording and editing device, and at least one touch gesture operating trajectory is correspondingly generated by the touch gesture recording and editing device. The touch gesture simulation device includes at least one artificial finger. The at least one artificial finger is driven and moved to an under-test touch object by the touch gesture simulation device. The at least one touch gesture is simulated by the touch gesture simulation device according to the at least one touch gesture operating trajectory.Type: GrantFiled: September 5, 2023Date of Patent: May 14, 2024Assignee: PRIMAX ELECTRONICS LTD.Inventors: Yung-Tai Pan, Jui-Hung Hsu, Chang-Ming Huang
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Publication number: 20240155425Abstract: The present disclosure relates to radio frame sending methods and apparatuses, and radio frame receiving methods and apparatuses. In one example method, a multi-link device generates a radio frame, where the radio frame includes a first multi-link element (MLE) and a second MLE, the first MLE includes a first information element, the second MLE includes a second information element, and the first information element and the second information element correspond to station information of a same link. Then, the multi-link device sends the radio frame.Type: ApplicationFiled: January 19, 2024Publication date: May 9, 2024Inventors: Yuchen GUO, Yiqing LI, Guogang HUANG, Yunbo LI, Ming GAN
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Publication number: 20240150192Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Pi CHANG, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Huang-Lin Chao
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Publication number: 20240153861Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.Type: ApplicationFiled: January 14, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Publication number: 20240151972Abstract: An augmented reality (AR) display is provided. The display comprises a light field generator and a birdbath eyepiece. The light field generator generates a light field as an output. The birdbath eyepiece connects to the light field generator for receiving and projecting the light field to human eye. The birdbath eyepiece comprises a beam splitter and a combiner. The combiner has a curved surface. Each beam of the light field is split into two beams by the beam splitter with one of the split beams reflected by the combiner. Three states-of-use of the birdbath eyepiece are provided for the near-eye light field AR display to transmit the light field to the human eye. A low f-number (or focal ratio) and a large eyebox are obtained to effectively expand the field of view and increase the volume of space within which the human eye can receive the light field.Type: ApplicationFiled: July 27, 2023Publication date: May 9, 2024Inventors: Chao-Chien Wu, Jiun-Woei Huang, Hong-Ming Chen
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Publication number: 20240150906Abstract: An electrolytic cell includes a cation exchange membrane, a cathode compartment, and an anode compartment. The cathode compartment includes a gas diffusion electrode and a flow channel element, in which the flow channel element is between the cation exchange membrane and the gas diffusion electrode, and has a plurality of flow channels arranged in parallel with each other. The anode compartment includes an anode mesh, in which the cation exchange membrane is between the anode mesh and the flow channel element. A distance between the anode mesh and the gas diffusion electrode is substantially equal to the sum of a first thickness of the cation exchange membrane and a second thickness of the flow channel element. The novel electrolytic cell can combine with a chloralkali electrolytic cell to deal with gaseous CO2 and produce products, e.g., synthesis gas, for other purposes.Type: ApplicationFiled: May 9, 2023Publication date: May 9, 2024Inventors: Hao-Ming CHEN, Tai-Lung CHEN, Wan-Tun HUNG, Yu-Cheng CHEN, Kuo-Ming HUANG, Fu-Da YEN, Che-Jui LIAO
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Publication number: 20240155717Abstract: A method includes: The non-AP MLD generates a buffer report, and sends the buffer report to the AP MLD on a first uplink/downlink of the plurality of uplinks/downlinks. The buffer report includes a request for a duration of direct transmission performed by a first affiliated non-AP STA of the non-AP MLD on a first direct link, the first direct link is a link between a first target non-AP STA and the first affiliated non-AP STA, and the first target non-AP STA and the first affiliated non-AP STA belong to a same BSS.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Inventors: Guogang HUANG, Yunbo LI, Yuchen GUO, Ming GAN, Yiqing LI
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Publication number: 20240152463Abstract: The invention provides a configurable memory system including an interface layer, an overlay application layer, and a memory relocatable layer. The interface layer has a physical memory attribute module and a physical memory protection module. The interface layer manages memory attributes and memory security. The overlay application layer is coupled to the interface layer and executes an exception handler process to check if an overlay exception has occurred. The memory relocatable layer, coupled to the interface layer and the overlay application layer, having a plurality of resident service program within a first memory space, an overlay physical region within a second memory space, and a plurality of overlay virtual regions having application processes within a third memory space. The application processes of one of the overlay virtual regions is determined to be executed by the PMA module and is copied from the overlay virtual region to the overlay physical region by a processor.Type: ApplicationFiled: November 9, 2022Publication date: May 9, 2024Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Chih-Ming Shen, Cheng-Yen Huang
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Patent number: 11978929Abstract: A close-end fuel cell and an anode bipolar plate thereof are provided. The anode bipolar plate includes an airtight conductive frame and a conductive porous substrate disposed within the airtight conductive frame. In the airtight conductive frame, an edge of a first side has a fuel inlet, and an edge of a second side has a fuel outlet. The conductive porous substrate has at least one flow channel, where a first end of the flow channel communicates with the fuel inlet, a second end of the flow channel communicates with the fuel outlet. The flow channel is provided with a blocking part near the fuel inlet to divide the flow channel into two areas.Type: GrantFiled: August 23, 2021Date of Patent: May 7, 2024Assignee: Industrial Technology Research InstituteInventors: Sung-Chun Chang, Chien-Ming Lai, Chiu-Ping Huang, Li-Duan Tsai, Keng-Yang Chen
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Patent number: 11978674Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.Type: GrantFiled: October 8, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Ming Chang, Jung-Hung Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Yao-Sheng Huang, Huang-Lin Chao
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Patent number: 11978669Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.Type: GrantFiled: January 4, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11977205Abstract: An optical element including an optically transparent lens which defines a curved surface having a steepness given by an R/# of from about 0.5 to about 1.0. A film is positioned on the curved surface. The film includes an index layer. A composite layer is positioned on the curved surface having a refractive index greater than the index layer. The composite layer includes HfO2 and Al2O3. The composite layer has a mole fraction X of HfO2, wherein X is from about 0.05 to about 0.95 and a mole fraction of Al2O3 in the composite layer is 1?X.Type: GrantFiled: April 1, 2022Date of Patent: May 7, 2024Assignee: Corning IncorporatedInventors: Ming-Huang Huang, Chang-gyu Kim, Hoon Kim, Soo Ho Park, Jue Wang
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Publication number: 20240145632Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.Type: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
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Publication number: 20240145255Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.Type: ApplicationFiled: September 14, 2023Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Ker-Yih KAO, Chin-Ming HUANG, Wei-Yuan CHENG, Jui-Jen YUEH, Kuan-Feng LEE
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Publication number: 20240145653Abstract: A manufacturing method of a display device includes forming light emitting components on a first substrate, the light emitting components include a first side and a second side, and the second side is away from the first substrate; forming a circuit layer on the first substrate and on the second side of the light emitting components; forming a first protective layer on the circuit layer and forming an insulating layer on the first protective layer; removing the first substrate after forming a second substrate on the insulating layer; forming a black matrix layer on the first side of the light emitting components, and the black matrix layer includes openings; forming light conversion layers in the openings of the black matrix layer; forming a second protective layer on the black matrix layer and the light conversion layers; and forming a third substrate on the second protective layer.Type: ApplicationFiled: May 12, 2023Publication date: May 2, 2024Applicant: HANNSTAR DISPLAY CORPORATIONInventors: Chun-I Chu, Yu-Chi Chiao, Yung-Li Huang, Hung-Ming Chang, Cheng-Yu Lin, Huan-Hsun Hsieh, CHeng-Pei Huang
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Patent number: 11972957Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.Type: GrantFiled: July 31, 2020Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-chun Yang, Chih-Lung Cheng, Yi-Ming Lin, Po-Chih Huang, Yu-Hsiang Juan, Xuan-Yang Zheng
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Patent number: 11972984Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.Type: GrantFiled: December 26, 2022Date of Patent: April 30, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
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Patent number: 11974342Abstract: This application discloses a multi-link establishment method and a related device. A multi-link association response frame carries radio bitmap information, to indicate an AP allowed to be associated with a radio of a STA MLD or a link allowed to be established by using a radio of a STA MLD, so that the radio subsequently switches between different APs or links. The multi-link association response frame carries link establishment status information, to indicate a link establishment status of each link that the STA MLD requests to establish, so that multi-link establishment is more flexible. The multi-link association response frame carries reassociation information, to indicate whether each parameter in association configuration information is reserved, so that a problem that signaling overheads are relatively large due to a reassociation operation is avoided. It can be learned that, in the multi-link establishment method, the foregoing information is carried to improve multi-link establishment flexibility.Type: GrantFiled: April 14, 2023Date of Patent: April 30, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Guogang Huang, Yunbo Li, Ming Gan, Yuchen Guo
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Patent number: 11974422Abstract: A semiconductor device includes a semiconductor substrate, ground level circuitry, a plurality of stacked memory arrays and a plurality of sense amplifier units. The ground level circuitry is disposed on the semiconductor substrate. The stacked memory arrays are disposed at an elevated level over the ground level circuitry. The sense amplifier units are disposed on the semiconductor substrate and electrically coupled to the stacked memory arrays, wherein at least a portion of each of the sense amplifier units is disposed at the elevated level over the ground level circuitry.Type: GrantFiled: February 10, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yu-Ming Lin