Abstract: According to an embodiment, an information processing device is configured to assign a first computing device one or more first tasks of processing respective one or more first partial data of a plurality of partial data included in an n-dimensional target data, n being an integer greater than or equal to 2, the target data being to be processed using a neural network, the one or more first partial data including first data and second data adjacent to the first data in a direction of m-dimension, m being an integer satisfying 1?m?n; and instruct the first computing device to execute a second task included in the one or more first tasks, according to an execution status of second partial data of the plurality of partial data included in the target data, the second partial data being executed by the second computing device.

Abstract: An information processing system according to an embodiment includes at least one supplementary information processing apparatus and a main information processing apparatus. The main information processing apparatus is connected to each of the at least one supplementary information processing apparatus via a communication network. The supplementary information processing apparatus executes, on input information, arithmetic processing using a preceding network from an input layer to a boundary layer located at a predetermined position in a first neural network, and transmits intermediate information indicating an arithmetic result of the arithmetic processing using the preceding network, to the main information processing apparatus. The main information processing apparatus executes, on the intermediate information, arithmetic processing using a succeeding network from a layer subsequent to the boundary layer to an output layer in the first neural network.

Abstract: An arithmetic processing device to realize a multi-layer convolutional neural network circuit to perform a process with fixed-point number format, according to an embodiment comprising: a processing circuitry and a memory, the processing circuitry conducting: a learning process to perform weight learning or bias learning using learning data stored the memory to calculate initial weight values and initial bias values of the multi-layer convolutional neural network circuit; a trial recognition process to perform a recognition process to part of the learning data or of input data using the initial weight values and the initial bias values; a processing treatment process to multiply the initial weight values and the initial bias values by a positive constant to calculate processed weight values or processed bias values; and a recognition process to perform a recognition process using the processed weight values and the processed bias values.

Abstract: A convolutional arithmetic processing device includes a convolutional arithmetic processor and a storage device. The convolutional arithmetic processor performs a first convolutional arithmetic process of a convolutional neural network on numerical values of a first three-dimensional array, using a type of kernel formed of numerical values of a second three-dimensional array, where a number of the type is represented by a second numerical value with a stride represented by a third numerical value in a first direction and a stride represented by a fourth numerical value in a second direction. The storage device stores at least part of the numerical values of the first three-dimensional array.

Abstract: An information processing system according to an embodiment includes at least one supplementary information processing apparatus and a main information processing apparatus. The main information processing apparatus is connected to each of the at least one supplementary information processing apparatus via a communication network. The supplementary information processing apparatus executes, on input information, arithmetic processing using a preceding network from an input layer to a boundary layer located at a predetermined position in a first neural network, and transmits intermediate information indicating an arithmetic result of the arithmetic processing using the preceding network, to the main information processing apparatus. The main information processing apparatus executes, on the intermediate information, arithmetic processing using a succeeding network from a layer subsequent to the boundary layer to an output layer in the first neural network.

Abstract: According to an embodiment, an information processing device is configured to assign a first computing device one or more first tasks of processing respective one or more first partial data of a plurality of partial data included in an n-dimensional target data, n being an integer greater than or equal to 2, the target data being to be processed using a neural network, the one or more first partial data including first data and second data adjacent to the first data in a direction of m-dimension, m being an integer satisfying 1?m?n; and instruct the first computing device to execute a second task included in the one or more first tasks, according to an execution status of second partial data of the plurality of partial data included in the target data, the second partial data being executed by the second computing device.

Abstract: According to an embodiment, an arithmetic processing device includes a reception unit, and a calculation unit. The reception unit is configured to receive a plurality of pairs each consisting of a first floating-point value output as an output result of first processing and a second floating-point value output as an output result of second processing. The calculation unit is configured to perform linear regression on the plurality of pairs and calculate a degree of similarity between output results of the first processing and output results of the second processing, based on information obtained by the linear regression.

Abstract: An arithmetic processing device according to the present embodiment includes: a first storage device including m (m?2) groups each including at least one first array; a second storage device including n (m>n?1) groups each including at least one second array; a third storage device including at least one third array; a fourth storage device including k (m>k?1) fourth arrays; and a processor, the processor selecting n groups of the first array from among the m groups of the first array, reading out data stored in memory elements of the first array included in the selected groups, storing the data in the memory elements of the second array of the second storage device, and the processor performing a convolution process to the third array using the data stored in the memory elements of the second array and storing a result of the convolution process in the fourth arrays.

Abstract: An arithmetic processing device according to the present embodiment includes: a first storage device including m (m?2) groups each including at least one first array; a second storage device including n (m>n?1) groups each including at least one second array; a third storage device including at least one third array; a fourth storage device including k (m>k?1) fourth arrays; and a processor, the processor selecting n groups of the first array from among the m groups of the first array, reading out data stored in memory elements of the first array included in the selected groups, storing the data in the memory elements of the second array of the second storage device, and the processor performing a convolution process to the third array using the data stored in the memory elements of the second array and storing a result of the convolution process in the fourth arrays.

Abstract: An arithmetic processing device to realize a multi-layer convolutional neural network circuit to perform a process with fixed-point number format, according to an embodiment comprising: a processing circuitry and a memory, the processing circuitry conducting: a learning process to perform weight learning or bias learning using learning data stored the memory to calculate initial weight values and initial bias values of the multi-layer convolutional neural network circuit; a trial recognition process to perform a recognition process to part of the learning data or of input data using the initial weight values and the initial bias values; a processing treatment process to multiply the initial weight values and the initial bias values by a positive constant to calculate processed weight values or processed bias values; and a recognition process to perform a recognition process using the processed weight values and the processed bias values.

Abstract: An arithmetic processing device according to an embodiment includes: a first storage device including a first array having memory elements arranged in a first direction and a second direction intersecting with the first direction; a second storage device including a second array having memory elements arranged in the first direction; a third storage device including a third array having memory elements arranged in the first and second directions, the third array having a smaller number of memory elements arranged in the first direction than the memory elements of the first array, arranged in the first direction, and having a smaller number of memory elements arranged in the second direction than the memory elements of the first array, arranged in the second direction; and a first process layer, using data stored in the memory elements of the third array, to perform a convolution process.

Abstract: A semiconductor device of an embodiment includes: a logical block including at least one first input terminal; at least two first output terminal; a first wiring line group; a second and third wiring line groups including a plurality of shorter wiring lines than wiring lines of the first wiring line group; a fourth and fifth wiring line groups; a first to fourth switch circuits; a first logical element including second and third input terminals connected to at least one of wiring lines of the fourth wiring line group, and a second output terminal connected to one of the at least two first output terminals; and a second logical element including fourth and fifth input terminals connected to at least one of the wiring lines of the fifth wiring line group, and a third output terminal connected to another of the at least two first output terminals.

Abstract: A semiconductor device of an embodiment includes: a logical block including at least one first input terminal; at least two first output terminal; a first wiring line group; a second and third wiring line groups including a plurality of shorter wiring lines than wiring lines of the first wiring line group; a fourth and fifth wiring line groups; a first to fourth switch circuits; a first logical element including second and third input terminals connected to at least one of wiring lines of the fourth wiring line group, and a second output terminal connected to one of the at least two first output terminals; and a second logical element including fourth and fifth input terminals connected to at least one of the wiring lines of the fifth wiring line group, and a third output terminal connected to another of the at least two first output terminals.

Abstract: A semiconductor component includes a mixed crystal layer of silicon and germanium having a first main surface, containing a III-group impurity, and having a first face orientation alone represented as a face (11N) by using N satisfying 1.2<N<10 or a face crystallographically equivalent to the face (11N) in the first main surface, a compressive strain being applied to the mixed crystal layer along an in-plane direction, a gate dielectric layer formed on the first main surface. The component further includes a gate electrode formed on the gate dielectric layer, and source/drain regions formed to sandwich the gate electrode in a direction [110] or a crystallographically equivalent direction of the mixed crystal layer and containing a V-group impurity.

Abstract: The channel of each nonvolatile semiconductor memory element has a plate-like shape, and a charge accumulating layer is formed on one face of the channel region, with an insulating film being interposed in between. A control gate electrode is then formed on the charge accumulating layer, with another insulating film being interposed in between. Another control gate electrode is formed on the other face of the channel region, with yet another insulating film being interposed in between. The plate-like semiconductor region is designed to have a thickness smaller than twice the largest depletion layer thickness determined by the impurity concentration. In this manner, variations of the threshold voltages varying with the voltage of the control gate electrodes can be made smaller than the minimum value in conventional elements.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: A semiconductor component includes an insulating region provided on the substrate, plural first conductivity type wire-form semiconductor layers aligned on the insulating region parallel to each other, second conductivity type source/drain regions provided to the respective semiconductor layers, a channel region provided between the source/drain regions, an insulating film provided on the upper and side surfaces of the channel region, and a gate electrode provided on the insulating film to continuously cross the semiconductor layers. The channel region length measured perpendicularly to a current flowing direction and in parallel to the substrate is not more than twofold a maximum depletion layer width determined based on an impurity concentration in the channel region, each interval between the semiconductor layers is not more than twofold an interval between the semiconductor layer and the gate electrode, and a dielectric constant of a part of the insulating region surface is lower than 3.9.

Abstract: A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer.

Abstract: A semiconductor component includes a mixed crystal layer of silicon and germanium having a first main surface, containing a III-group impurity, and having a first face orientation alone represented as a face (11N) by using N satisfying 1.2<N<10 or a face crystallographically equivalent to the face (11N) in the first main surface, a compressive strain being applied to the mixed crystal layer along an in-plane direction, a gate dielectric layer formed on the first main surface. The component further includes a gate electrode formed on the gate dielectric layer, and source/drain regions formed to sandwich the gate electrode in a direction [110] or a crystallographically equivalent direction of the mixed crystal layer and containing a V-group impurity.

Abstract: A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the second wiring line group being arranged in parallel with each other and being movable in the vicinity of each intersection with the wiring lines of the first wiring line group, and a plurality of metal regions which are formed to be joined with the wiring lines constituting the second wiring line group, and have a work function different from that of the metal forming the first wiring line group.