Patents by Inventor Mizuki Ono
Mizuki Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060289996Abstract: A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the second wiring line group being arranged in parallel with each other and being movable in the vicinity of each intersection with the wiring lines of the first wiring line group, and a plurality of metal regions which are formed to be joined with the wiring lines constituting the second wiring line group, and have a work function different from that of the metal forming the first wiring line group.Type: ApplicationFiled: December 27, 2005Publication date: December 28, 2006Inventors: Mizuki Ono, Yuichi Motoi
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Patent number: 7087969Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.Type: GrantFiled: January 21, 2004Date of Patent: August 8, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Akira Nishiyama, Mizuki Ono, Masato Koyama, Takamitsu Ishihara
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Publication number: 20060081851Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.Type: ApplicationFiled: October 6, 2005Publication date: April 20, 2006Inventor: Mizuki Ono
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Publication number: 20060063319Abstract: A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer.Type: ApplicationFiled: June 6, 2005Publication date: March 23, 2006Inventor: Mizuki Ono
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Publication number: 20050224898Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed an the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 ?m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined a be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: June 3, 2005Publication date: October 13, 2005Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 6929990Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 ?m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: October 9, 2003Date of Patent: August 16, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20050051856Abstract: The semiconductor device includes a gate insulator with a three-layer stacked structure including a first insulator on a semiconductor substrate, a second insulator on the first insulator, and a third insulator on the second insulator. The first insulator is made of silicon oxide, silicon nitride, or oxinitrided silicon. The second and the third insulator contain a metal. The dielectric constant of the second insulator is higher than the square root of the product of the dielectric constants of the first and the third insulator. The present invention provides a high-speed semiconductor device, decreasing scattering of the carriers.Type: ApplicationFiled: July 2, 2004Publication date: March 10, 2005Inventors: Mizuki Ono, Takamitsu Ishihara
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Publication number: 20050040461Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.Type: ApplicationFiled: September 29, 2004Publication date: February 24, 2005Inventors: Mizuki Ono, Akira Nishiyama
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Patent number: 6847084Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.Type: GrantFiled: August 1, 2003Date of Patent: January 25, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Mizuki Ono, Akira Nishiyama
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Publication number: 20040207023Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.Type: ApplicationFiled: January 21, 2004Publication date: October 21, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira Nishiyama, Mizuki Ono, Masato Koyama, Takamitsu Ishihara
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Patent number: 6724025Abstract: A semiconductor device comprises a channel of a first conductive type formed on a surface layer of a semiconductor substrate, source and a drain of a second conductive type formed on both sides of the channel, a gate insulation film with a first relative permittivity formed at least on the channel directly or through a buffer insulation film, a gate electrode formed on the gate insulation film, and a side insulation film formed at least on a side of the gate insulation film and having a second relative permittivity which is smaller than the first relative permittivity, and, when assuming that an area of the gate insulation film, which is adjacent to the surface layer on a gate electrode side, is S1, and an area thereof, which is adjacent to the surface layer on the channel side, is S2, the area S1 is larger than the area S2.Type: GrantFiled: June 29, 1999Date of Patent: April 20, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Daisaburo Takashima, Mizuki Ono
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Publication number: 20040070024Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m: and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: October 9, 2003Publication date: April 15, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20040046227Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.Type: ApplicationFiled: August 1, 2003Publication date: March 11, 2004Inventors: Mizuki Ono, Akira Nishiyama
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Patent number: 6690047Abstract: In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode.Type: GrantFiled: April 26, 2002Date of Patent: February 10, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Yukihito Oowaki, Mizuki Ono, Mitsuhiro Noguchi, Daisaburo Takashima, Akira Nishiyama
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Patent number: 6642575Abstract: A field-effect transistor has a vertical columnar structure to restrain a short channel effect without impairing the operating speed of an element. In a semiconductor device having a field-effect transistor with a vertical columnar structure, an n-type diffusion layer region is formed in a surface layer of a p-type silicon substrate. A columnar structure portion is formed in which an n-type silicon layer, a buried insulation film and an n-type silicon layer are stacked over the n-type diffusion layer region and the buried insulation film is set back inward from both silicon layers. A silicon layer is formed over the side surface of the columnar structure portion, and a gate electrode is formed over the surface of the silicon layer with a gate insulation film that is interposed therebetween.Type: GrantFiled: December 3, 1999Date of Patent: November 4, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Mizuki Ono, Akira Toriumi
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Patent number: 6642560Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: June 4, 2002Date of Patent: November 4, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 6495890Abstract: A field-effect transistor comprises a semiconductor substrate, a gate insulation film formed selectively on the semiconductor substrate, a gate electrode formed on the gate insulation film, source/drain regions formed in surface portions of the semiconductor substrate along mutually opposed side surfaces of the gate electrode, the source/drain regions having opposed end portions located immediately below the gate electrode, each of the opposed end portions having an overlapping region which overlaps the gate electrode, and a channel region formed in a surface portion of the semiconductor substrate, which is sandwiched between the opposed source/drain regions. That portion of the gate insulation film, which is located at the overlapping region where at least one of the source/drain regions overlaps the gate electrode, has a lower dielectric constant than that portion of the gate insulation film, which is located on the channel region.Type: GrantFiled: August 31, 2000Date of Patent: December 17, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Mizuki Ono
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Publication number: 20020145157Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or lass than 0.3 &mgr;m and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.3 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: June 4, 2002Publication date: October 10, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Publication number: 20020117725Abstract: In a MIS transistor , the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode.Type: ApplicationFiled: April 26, 2002Publication date: August 29, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Yukihito Oowaki, Mizuki Ono, Mitsuhiro Noguchi, Daisaburo Takashima, Akira Nishiyama
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Patent number: 6410952Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: April 9, 2001Date of Patent: June 25, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura