Abstract: A non-volatile semiconductor memory element includes: a semiconductor region of a first conductivity type formed in a plate-like form on a semiconductor substrate; a first insulating film formed on a first side face of the semiconductor region; a first charge accumulating layer formed on a face of the first insulating film opposite from the semiconductor region; a second insulating film formed on a second side face of the semiconductor region, and has a different equivalent oxide thickness from the first insulating film; a second charge accumulating layer formed on a face of the second insulating film opposite from the semiconductor region; a third insulating film provided so as to cover the first and second charge accumulating layers; a control gate electrode provided so as to cover the third insulating film; a channel region formed in a portion of the semiconductor region covered with the control gate electrode; and source/drain regions of a second conductivity type formed in portions of the semiconductor r

Abstract: A semiconductor component includes an insulating region provided on the substrate, plural first conductivity type wire-form semiconductor layers aligned on the insulating region parallel to each other, second conductivity type source/drain regions provided to the respective semiconductor layers, a channel region provided between the source/drain regions, an insulating film provided on the upper and side surfaces of the channel region, and a gate electrode provided on the insulating film to continuously cross the semiconductor layers. The channel region length measured perpendicularly to a current flowing direction and in parallel to the substrate is not more than twofold a maximum depletion layer width determined based on an impurity concentration in the channel region, each interval between the semiconductor layers is not more than twofold an interval between the semiconductor layer and the gate electrode, and a dielectric constant of a part of the insulating region surface is lower than 3.9.

Abstract: A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: A memory element includes: a semiconductor region formed in a semiconductor substrate; source and drain regions formed at a distance from each other in the semiconductor region; a first insulating layer formed on the semiconductor region between the source and drain regions; a charge accumulating layer formed on the first insulating layer, and having a stacked structure including at least three conductor films and inter-conductor insulating films provided between the adjacent conductor films, a dielectric constant of any one of the inter-conductor insulating films located at a greater distance from the semiconductor substrate being higher than that of any one of the inter-conductor insulating films closer to the semiconductor substrate, a dielectric constant of each of the inter-conductor insulating films being lower than that of the first insulating layer; and a second insulating layer formed on the charge accumulating layer, and having a higher dielectric constant than that of any one of the inter-conductor

Abstract: A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Abstract: The channel of each nonvolatile semiconductor memory element has a plate-like shape, and a charge accumulating layer is formed on one face of the channel region, with an insulating film being interposed in between. A control gate electrode is then formed on the charge accumulating layer, with another insulating film being interposed in between. Another control gate electrode is formed on the other face of the channel region, with yet another insulating film being interposed in between. The plate-like semiconductor region is designed to have a thickness smaller than twice the largest depletion layer thickness determined by the impurity concentration. In this manner, variations of the threshold voltages varying with the voltage of the control gate electrodes can be made smaller than the minimum value in conventional elements.

Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 ?m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

Abstract: In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode.

Abstract: A semiconductor element includes: a semiconductor region formed in a semiconductor substrate and containing an impurity of a predetermined conductivity type; source and drain regions formed to face each other in the semiconductor region, and containing a metal or a compound of a metal and a semiconductor forming the semiconductor region; a channel region located in the semiconductor region between the source region and the drain region; an insulating film covering the channel region and a part of each of the source and drain regions; and a gate electrode formed on the insulating film. A first portion of an interface between the insulating film and the gate electrode that is located above an at least partial region of the channel region exists closer to the semiconductor region than a second portion of the interface between the insulating film and the gate electrode located above each junction between the channel region and the source and drain regions.

Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed an the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 ?m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined a be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

Abstract: A highly-integrated, high-performance semiconductor device with a simplest possible structure can be provided.

Abstract: It is made possible to provide a highly-reliable, high-performance semiconductor device that reduces the intensity of the electric field in the gate insulating film, has a higher current driving force, and can operate at a high speed. A semiconductor device includes: a semiconductor region provided on a substrate; source and drain regions provided in the semiconductor region at a distance from each other so as to face each other; a semiconductor layer provided on the source and drain regions and a region interposed between the source region and the drain region; a gate insulating film provided at least above the region interposed between the source region and the drain region so as to sandwich the semiconductor layer between the gate insulating film and the region interposed between the source region and the drain region; and a gate electrode provided on the gate insulating film.

Abstract: A non-volatile semiconductor memory element includes: a semiconductor region of a first conductivity type formed in a plate-like form on a semiconductor substrate; a first insulating film formed on a first side face of the semiconductor region; a first charge accumulating layer formed on a face of the first insulating film opposite from the semiconductor region; a second insulating film formed on a second side face of the semiconductor region, and has a different equivalent oxide thickness from the first insulating film; a second charge accumulating layer formed on a face of the second insulating film opposite from the semiconductor region; a third insulating film provided so as to cover the first and second charge accumulating layers; a control gate electrode provided so as to cover the third insulating film; a channel region formed in a portion of the semiconductor region covered with the control gate electrode; and source/drain regions of a second conductivity type formed in portions of the semiconductor r

Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

Abstract: A semiconductor device includes a semiconductor layer, a pair of a source region and a drain region formed to face each other in a direction on the semiconductor layer and made of a metal or a metal silicide, a first dielectric film formed on at least the semiconductor layer between the source region and the drain region, a second dielectric film formed on the first dielectric film and having a dielectric constant higher than that of the first dielectric film, and a gate electrode formed on the second dielectric film. A length of the second dielectric film measured in the direction is shorter than that of the gate electrode measured in the direction.