Abstract: Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.

Abstract: A vapor deposition system can include a first portion of the vapor deposition system that is configured to be purged using a first material and a second portion that is configured to be purged using a second material. Related methods are also disclosed.

Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Abstract: Forming a ferroelectric memory device can include forming an insulating layer on a substrate, forming a sacrificial layer on the first insulating layer so that the insulating layer is between the sacrificial layer and the substrate, and forming a contact hole extending through the sacrificial layer and the insulating layer. A conductive contact plug can be formed in the contact hole. After forming the conductive contact plug in the contact hole, the sacrificial layer can be removed so that the conductive contact plug extends beyond the insulating layer, and so that sidewalls of the conductive contact plug extending beyond the insulating layer are exposed. A first electrode can be formed on exposed portions of the conductive contact plug, a ferroelectric layer can be formed on the first electrode, and a second electrode can be formed on the ferroelectric layer such that the ferroelectric layer is between the first and second electrodes. Related structures are also discussed.

Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The device includes a substrate where a conductive region is formed and an interlayer insulating layer. The interlayer insulating layer is stacked on the substrate and has a contact hole exposing the conductive region. The contact hole is filled with a contact plug having a projection over the interlayer insulating layer. The projection of the contact plug is covered with a capacitor including a lower electrode, a ferroelectric layer pattern, and an upper electrode. A width of the projection is preferably greater than that of the contact hole and smaller than that of the lower electrode. The method includes forming lower and upper interlayer insulating layers on a substrate where a conductive region is formed. The lower and upper interlayer insulating layers have a contact hole exposing the conductive region.

Abstract: A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to reduce a resistance of the transition metal oxide layer and applying a second electric pulse to the transition metal oxide layer for a second period, longer than the first period, to increase the resistance of the transition metal oxide layer. Related devices are also disclosed.

Abstract: A cross-point nonvolatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines disposed in a substrate. Spaced apart upper electrodes cross over the doped lines such that cross points are formed where the upper electrodes overlap the doped lines. Lower electrodes are disposed at the cross points between the doped lines and the upper electrodes. A binary metal oxide layer is provided between the upper electrodes and the lower electrodes and provided as a data storage material layer. Doped regions are provided between the lower electrodes and the doped lines and form diodes together with the doped lines.

Abstract: Integrated circuit devices and methods of fabricating the same include an interlayer dielectric formed on an integrated circuit substrate. A plurality of buried contacts are formed in the interlayer dielectric and an oxide layer is formed on the interlayer dielectric. An intaglio pattern is formed in the oxide layer that exposes the plurality of buried contacts and a plurality of lower electrodes are formed within a single opening in the intaglio pattern. The lower electrodes are in electrical contact with corresponding ones of the buried contacts. The lower electrodes may be formed symmetrically in the intaglio pattern and may be semi-cylindrical electrodes. The integrated circuit device may be a ferroelectric memory device and forming a plurality of lower electrodes may include forming a plurality of capacitors.

Abstract: Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided between the lower and upper electrodes. The transition metal oxide layer pattern is represented by a chemical formula MxOy. In the chemical formula, the characters “M”, “O”, “x” and “y” indicate transition metal, oxygen, a transitional metal composition and an oxygen composition, respectively. The transition metal oxide layer pattern has excessive transition metal content in comparison to a stabilized transition metal oxide layer pattern. Methods of fabricating the non-volatile memory cells are also provided.

Abstract: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned with the node contact holes, respectively, and are disposed so as to protrude upward from the diffusion preventive layer. Lower electrodes are disposed on the diffusion preventive layer that cover the node conductive layer patterns, respectively. Thicknesses of the lower electrodes are gradually reduced from a line extending from upper surfaces of the node conductive layer patterns toward the diffusion preventive layer.

Abstract: A method of forming a ferroelectric capacitor includes forming a lower electrode on a substrate. The lower electrode is oxidized to form a metal oxide film. A ferroelectric film is formed on the metal oxide film while reduction of the oxygen content of the metal oxide film is inhibited. An upper electrode is formed on the ferroelectric film.

Abstract: Showerheads including a plate having a plurality of gas outlet holes extending therethrough and a head cover coupled to the plate to form a space between the plate and the head cover. A gas supply inlet member is configured to provide gas to the space directed toward the head cover. A gas distribution member on an inner face of the head cover facing the space is configured to partially suppress flow of the gas provided to the space in a direction along the gas distribution member to substantially uniformly distribute the gas in the space. The direction along the gas distribution member may be a horizontal direction and the gas provided to the space is directed in a substantially vertical upward direction. Apparatus and methods using the showerheads are also provided.

Abstract: A method of forming a ferroelectric capacitor includes forming a lower electrode on a substrate. The lower electrode is oxidized to form a metal oxide film. A ferroelectric film is formed on the metal oxide film while reduction of the oxygen content of the metal oxide film is inhibited. An upper electrode is formed on the ferroelectric film.

Abstract: A method of forming a ferroelectric capacitor includes forming a lower electrode on a substrate. The lower electrode is oxidized to form a metal oxide film. A ferroelectric film is formed on the metal oxide film while reduction of the oxygen content of the metal oxide film is inhibited. An upper electrode is formed on the ferroelectric film.

Abstract: Metal organic chemical vapor deposition (MOCVD) may be utilized in methods of forming an (111) oriented PZT ferroelectric layer at a lower temperature, a ferroelectric capacitor and methods of fabricating, and a ferroelectric memory device using the same may be provided. Using the metal organic chemical vapor deposition, ferroelectric layers, capacitors, and memory devices, which may be fabricated and may have (111) preferred oriented crystal growth.

Abstract: Ferroelectric capacitors, etc. are disclosed that include a conductive plug that has a base portion of a first cross-sectional width and a protruding portion that protrudes from the base portion and has a second cross-sectional width that is less than the first cross-sectional width. A conductive layer of the ferroelectric capacitor is on the protruding portion opposite the base portion. Related methods are also disclosed.

Abstract: Methods and apparatus for depositing a layer including providing at least one precursor vapor to a process chamber, providing a gas to the process chamber, separate from the at least one precursor vapor, and forming a compound layer from the at least one precursor vapor and the gas on a wafer in the process chamber. The deposition may be a chemical vapor deposition (CVD) deposition method, a metal organic chemical vapor deposition (MOCVD) deposition method, an atomic layer deposition (ALD) deposition method, or other similar deposition method. The compound layer may be at least one of an oxide, nitride, carbide, or other similar layer.

Abstract: A vapor deposition system can include a first portion of the vapor deposition system that is configured to be purged using a first material and a second portion that is configured to be purged using a second material. Related methods are also disclosed.