Abstract: Integrated circuit devices and methods of fabricating the same include an interlayer dielectric formed on an integrated circuit substrate. A plurality of buried contacts are formed in the interlayer dielectric and an oxide layer is formed on the interlayer dielectric. An intaglio pattern is formed in the oxide layer that exposes the plurality of buried contacts and a plurality of lower electrodes are formed within a single opening in the intaglio pattern. The lower electrodes are in electrical contact with corresponding ones of the buried contacts. The lower electrodes may be formed symmetrically in the intaglio pattern and may be semi-cylindrical electrodes. The integrated circuit device may be a ferroelectric memory device and forming a plurality of lower electrodes may include forming a plurality of capacitors.

Abstract: An apparatus for fabricating a semiconductor device in which a substance is deposited on a semiconductor wafer. The apparatus includes a heating arrangement and/or a shower head arrangement. The shower head arrangement supplies at least two source gases to the apparatus. The heating arrangement heats at least one of the source gases supplied to a process chamber of the apparatus. The heating arrangement may include a heat pipe including at least one part. A method of reducing thermal disturbance during fabrication of a semiconductor device using the heating arrangement and a method of exchanging heat during fabrication of the semiconductor device using the heating arrangement.

Abstract: The present invention discloses a method of forming a ferroelectric random access memory (FRAM) of a capacitor over bit-line (COB) structure. In the method, a capacitor contact plug is formed at a cell region and a stud is formed at a core region in a semiconductor substrate. An oxygen barrier pattern is formed to cover the stud. A ferroelectric capacitor comprising a lower electrode, a ferroelectric pattern, and an upper electrode is formed over the capacitor contact plug. An interlayer dielectric layer is formed over substantially the entire surface of the semiconductor substrate and patterned. Next, the interlayer dielectric layer is removed from the stud region and an interconnection contact hole is formed. A contact plug is formed in the interconnection contact hole by sputtering and simultaneously an interconnection layer is formed on the interlayer dielectric layer.

Abstract: A method of forming a ferroelectric capacitor includes forming a lower electrode on a substrate. The lower electrode is oxidized to form a metal oxide film. A ferroelectric film is formed on the metal oxide film while reduction of the oxygen content of the metal oxide film is inhibited. An upper electrode is formed on the ferroelectric film.

Abstract: Ferroelectric capacitors, etc. are disclosed that include a conductive plug that has a base portion of a first cross-sectional width and a protruding portion that protrudes from the base portion and has a second cross-sectional width that is less than the first cross-sectional width. A conductive layer of the ferroelectric capacitor is on the protruding portion opposite the base portion. Related methods are also disclosed.

Abstract: Ferroelectric capacitors, etc. are disclosed that include a conductive plug that has a base portion of a first cross-sectional width and a protruding portion that protrudes from the base portion and has a second cross-sectional width that is less than the first cross-sectional width. A conductive layer of the ferroelectric capacitor is on the protruding portion opposite the base portion. Related methods are also disclosed.

Abstract: Forming a ferroelectric memory device can include forming an insulating layer on a substrate, forming a sacrificial layer on the first insulating layer so that the insulating layer is between the sacrificial layer and the substrate, and forming a contact hole extending through the sacrificial layer and the insulating layer. A conductive contact plug can be formed in the contact hole. After forming the conductive contact plug in the contact hole, the sacrificial layer can be removed so that the conductive contact plug extends beyond the insulating layer, and so that sidewalls of the conductive contact plug extending beyond the insulating layer are exposed. A first electrode can be formed on exposed portions of the conductive contact plug, a ferroelectric layer can be formed on the first electrode, and a second electrode can be formed on the ferroelectric layer such that the ferroelectric layer is between the first and second electrodes. Related structures are also discussed.

Abstract: The present invention discloses a method of forming a ferroelectric random access memory (FRAM) of a capacitor over bit-line (COB) structure. In the method, a capacitor contact plug is formed at a cell region and a stud is formed at a core region in a semiconductor substrate. An oxygen barrier pattern is formed to cover the stud. A ferroelectric capacitor comprising a lower electrode, a ferroelectric pattern, and an upper electrode is formed over the capacitor contact plug. An interlayer dielectric layer is formed over substantially the entire surface of the semiconductor substrate and patterned. Next, the interlayer dielectric layer is removed from the stud region and an interconnection contact hole is formed. A contact plug is formed in the interconnection contact hole by sputtering and simultaneously an interconnection layer is formed on the interlayer dielectric layer.