Patents by Inventor Motoyasu Terao
Motoyasu Terao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8618523Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.Type: GrantFiled: May 31, 2006Date of Patent: December 31, 2013Assignee: Renesas Electronics CorporationInventors: Norikatsu Takaura, Yuichi Matsui, Motoyasu Terao, Yoshihisa Fujisaki, Nozomu Matsuzaki, Kenzo Kurotsuchi, Takahiro Morikawa
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Patent number: 8513640Abstract: On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.Type: GrantFiled: November 14, 2006Date of Patent: August 20, 2013Assignee: Renesas Electronics CorporationInventors: Takahiro Morikawa, Motoyasu Terao, Norikatsu Takaura, Kenzo Kurotsuchi
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Patent number: 8482997Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: GrantFiled: February 5, 2012Date of Patent: July 9, 2013Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 8319204Abstract: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.Type: GrantFiled: July 21, 2006Date of Patent: November 27, 2012Assignee: Renesas Electronics CorporationInventors: Motoyasu Terao, Satoru Hanzawa, Takahiro Morikawa, Kenzo Kurotsuchi, Riichiro Takemura, Norikatsu Takaura, Nozomu Matsuzaki
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Publication number: 20120135548Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: ApplicationFiled: February 5, 2012Publication date: May 31, 2012Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 8130575Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: GrantFiled: August 11, 2011Date of Patent: March 6, 2012Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 8132063Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.Type: GrantFiled: July 26, 2011Date of Patent: March 6, 2012Assignee: Hitachi, Ltd.Inventors: Motoyasu Terao, Satoru Hanzawa, Hitoshi Kume, Minoru Ogushi, Yoshitaka Sasago, Masaharu Kinoshita, Norikatsu Takaura
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Patent number: 8129707Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.Type: GrantFiled: June 18, 2009Date of Patent: March 6, 2012Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Motoyasu Terao, Kenzo Kurotsuchi, Tsuyoshi Yamauchi
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Publication number: 20110292722Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogcnidc material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Publication number: 20110283039Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.Type: ApplicationFiled: July 26, 2011Publication date: November 17, 2011Inventors: MOTOYASU TERAO, Satoru Hanzawa, Hitoshi Kume, Minoru Ogushi, Yoshitaka Sasago, Masaharu Kinoshita, Norikatsu Takaura
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Patent number: 8000126Abstract: A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.Type: GrantFiled: January 11, 2007Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Takahiro Morikawa, Motoyasu Terao, Norikatsu Takaura, Kenzo Kurotsuchi, Nozomu Matsuzaki, Yoshihisa Fujisaki, Masaharu Kinoshita, Yuichi Matsui
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Patent number: 7995082Abstract: A recording medium including a plurality of recording layers, including: an optional first recording layer on which a light spot at a diffraction limit is formed; and a second recording layer on which a mark string pattern is formed, said second recording layer being different from said first recording layer, wherein when said mark string pattern is formed on a light receiving plane, while information of said first recording layer is reproduced, assuming that an optical distance between said first and second recording layers is dm, an optical distance d between optional two recording layers among a plurality of said recording layers is different from said dm.Type: GrantFiled: July 23, 2007Date of Patent: August 9, 2011Assignee: Hitachi, Ltd.Inventors: Hisataka Sugiyama, Takeshi Maeda, Kiyoshi Matsumoto, Motoyasu Terao, Shigenori Okamine, Tetsuya Nishida, Harukazu Miyamoto
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Patent number: 7996735Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.Type: GrantFiled: May 21, 2009Date of Patent: August 9, 2011Assignee: Hitachi, Ltd.Inventors: Motoyasu Terao, Satoru Hanzawa, Hitoshi Kume, Minoru Ogushi, Yoshitaka Sasago, Masaharu Kinoshita, Norikatsu Takaura
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Publication number: 20110110150Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: ApplicationFiled: January 18, 2011Publication date: May 12, 2011Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Sean
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Patent number: 7911910Abstract: Recording information is disclosed in which an information recording medium is irradiated with a recording energy beam that is power-modulated into at least a record power level and a record-ready power level lower than the record power level. The information is recorded on the recording medium in the form of length and interval of a mark portion. When forming a mark portion of a predetermined length, the radiation energy of the energy beam is increased as compared with when forming a mark portion of a different length before or after the first pulse of an energy beam pulse train including at least a pulse for forming the mark portion.Type: GrantFiled: July 21, 2008Date of Patent: March 22, 2011Assignee: Hitachi, Ltd.Inventors: Makoto Miyamoto, Tsuyoshi Toda, Masatoshi Ohtake, Motoyasu Terao, Junko Ushiyama, Keikichi Andoo, Yumiko Anzai, Akemi Hirotsune, Tetsuya Nishida, Hideki Saga
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Patent number: 7907491Abstract: Recording information is disclosed in which an information recording medium is irradiated with a recording energy beam that is power-modulated into at least a record power level and a record-ready power level lower than the record power level. The information is recorded on the recording medium in the form of length and interval of a mark portion. When forming a mark portion of a predetermined length, the radiation energy of the energy beam is increased as compared with when forming a mark portion of a different length before or after the first pulse of an energy beam pulse train including at least a pulse for forming the mark portion.Type: GrantFiled: July 21, 2008Date of Patent: March 15, 2011Assignee: Hitachi, Ltd.Inventors: Makoto Miyamoto, Tsuyoshi Toda, Masatoshi Ohtake, Motoyasu Terao, Junko Ushiyama, Keikichi Andoo, Yumiko Anzai, Akemi Hirotsune, Tetsuya Nishida, Hideki Saga
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Patent number: 7907490Abstract: Recording information is disclosed in which an information recording medium is irradiated with a recording energy beam that is power-modulated into at least a record power level and a record-ready power level lower than the record power level. The information is recorded on the recording medium in the form of length and interval of a mark portion. When forming a mark portion of a predetermined length, the radiation energy of the energy beam is increased as compared with when forming a mark portion of a different length before or after the first pulse of an energy beam pulse train including at least a pulse for forming the mark portion.Type: GrantFiled: July 21, 2008Date of Patent: March 15, 2011Assignee: Hitachi, Ltd.Inventors: Makoto Miyamoto, Tsuyoshi Toda, Masatoshi Ohtake, Motoyasu Terao, Junko Ushiyama, Keikichi Andoo, Yumiko Anzai, Akemi Hirotsune, Tetsuya Nishida, Hideki Saga
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Publication number: 20110049454Abstract: In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.Type: ApplicationFiled: June 23, 2006Publication date: March 3, 2011Inventors: Motoyasu Terao, Yuichi Matsui, Tsuyoshi Koga, Nozomu Matsuzaki, Norikatsu Takaura, Yoshihisa Fujisaki, Kenzo Kurotsuchi, Takahiro Morikawa, Yoshitaka Sasago, Junko Ushiyama, Akemi Hirotsune
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Patent number: 7894232Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: GrantFiled: April 21, 2009Date of Patent: February 22, 2011Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 7852727Abstract: Recording information is disclosed in which an information recording medium is irradiated with a recording energy beam that is power-modulated into at least a record power level and a record-ready power level lower than the record power level. The information is recorded on the recording medium in the form of length and interval of a mark portion. When forming a mark portion of a predetermined length, the radiation energy of the energy beam is increased as compared with when forming a mark portion of a different length before or after the first pulse of an energy beam pulse train including at least a pulse for forming the mark portion.Type: GrantFiled: March 28, 2008Date of Patent: December 14, 2010Assignee: Hitachi, Ltd.Inventors: Makoto Miyamoto, Tsuyoshi Toda, Masatoshi Ohtake, Motoyasu Terao, Junko Ushiyama, Keikichi Andoo, Yumiko Anzai, Akemi Hirotsune, Tetsuya Nishida, Hideki Saga