Patents by Inventor Motoyasu Terao
Motoyasu Terao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7838379Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.Type: GrantFiled: January 29, 2009Date of Patent: November 23, 2010Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Motoyasu Terao, Hideyuki Matsuoka, Yoshitaka Sasago, Yoshinobu Kimura, Akio Shima, Mitsuharu Tai, Norikatsu Takaura
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Patent number: 7834337Abstract: A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145° C. or higher. The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40 at % or more and 65 at % or less in Zn-Ge-Te.Type: GrantFiled: December 20, 2004Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Norikatsu Takaura, Motoyasu Terao, Hideyuki Matsuoka, Kenzo Kurotsuchi
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Patent number: 7829930Abstract: A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal.Type: GrantFiled: July 9, 2008Date of Patent: November 9, 2010Assignee: Hitachi, Ltd.Inventors: Motoyasu Terao, Hideyuki Matsuoka, Naohiko Irie, Yoshitaka Sasago, Riichiro Takemura, Norikatsu Takaura
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Patent number: 7767997Abstract: A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.Type: GrantFiled: July 9, 2008Date of Patent: August 3, 2010Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Motoyasu Terao, Norikatsu Takaura, Yoshihisa Fujisaki, Tomoyuki Kodama, Nobuyuki Arasawa
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Publication number: 20100188877Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.Type: ApplicationFiled: March 26, 2010Publication date: July 29, 2010Inventors: Satoru Hanzawa, Kiyoo Itoh, Hideyuki Matsuoka, Motoyasu Terao, Takeshi Sakata
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Publication number: 20100171087Abstract: In a semiconductor device including a phase change memory element whose memory layer is formed of a phase change material of M (additive element)-Ge (germanium)-Sb (antimony)-Te (tellurium), both of high heat resistance and stable data retention property are achieved. The memory layer has a fine structure with a different composition ratio therein, and an average composition of M?GeXSbYTeZ forming the memory layer satisfies the relations of 0???0.4, 0.04?X?0.4, 0?Y?0.3, 0.3?Z?0.6, and 0.03?(?+Y).Type: ApplicationFiled: May 21, 2007Publication date: July 8, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kenzo Kurotsuchi, Motoyasu Terao, Takahiro Morikawa, Norikatsu Takaura
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Patent number: 7719870Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.Type: GrantFiled: October 25, 2007Date of Patent: May 18, 2010Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Kiyoo Itoh, Hideyuki Matsuoka, Motoyasu Terao, Takeshi Sakata
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Publication number: 20100096613Abstract: A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.Type: ApplicationFiled: January 11, 2007Publication date: April 22, 2010Inventors: Takahiro Morikawa, Motoyasu Terao, Norikatsu Takaura, Kenzo Kurotsuchi, Nozomu Matsuzaki, Yoshihisa Fujisaki, Masaharu Kinoshita, Yuichi Matsui
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Publication number: 20100072451Abstract: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.Type: ApplicationFiled: July 21, 2006Publication date: March 25, 2010Inventors: Motoyasu Terao, Satoru Hanzawa, Takahiro Morikawa, Kenzo Kurotsuchi, Riichiro Takemura, Norikatsu Takaura, Nozomu Matsuzaki
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Patent number: 7684301Abstract: Recording information is disclosed in which an information recording medium is irradiated with a recording energy beam that is power-modulated into at least a record power level and a record-ready power level lower than the record power level. The information is recorded on the recording medium in the form of length and interval of a mark portion. When forming a mark portion of a predetermined length, the radiation energy of the energy beam is increased as compared with when forming a mark portion of a different length before or after the first pulse of an energy beam pulse train including at least a pulse for forming the mark portion.Type: GrantFiled: March 28, 2008Date of Patent: March 23, 2010Assignee: Hitachi, Ltd.Inventors: Makoto Miyamoto, Tsuyoshi Toda, Masatoshi Ohtake, Motoyasu Terao, Junko Ushiyama, Keikichi Andoo, Yumiko Anzai, Akemi Hirotsune, Tetsuya Nishida, Hideki Saga
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Publication number: 20100058127Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.Type: ApplicationFiled: May 21, 2009Publication date: March 4, 2010Inventors: Motoyasu TERAO, Satoru HANZAWA, Hitoshi KUME, Minoru OGUSHI, Yoshitaka SASAGO, Masaharu KINOSHITA, Norikatsu TAKAURA
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Patent number: 7667218Abstract: Disclosed herein is a phase change memory semiconductor integrated circuit device using a chalcogenide film that solves a problem that the operation temperature capable of ensuring long time memory retention is low due to low phase change temperature is and, at the same time, a problem that power consumption of the device is high since a large current requires to rewrite memory information due to low resistance. A portion of constituent elements for a chalcogenide comprises nitride, oxide or carbide which are formed to the boundary between the chalcogenide film and a metal plug as an underlying electrode and to the grain boundary of chalcogenide crystals thereby increasing the phase change temperature and high Joule heat can be generated even by a small current by increasing the resistance of the film.Type: GrantFiled: November 30, 2005Date of Patent: February 23, 2010Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Norikatsu Takaura, Yuichi Matsui, Nozomu Matsuzaki, Kenzo Kurotsuchi, Motoyasu Terao
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Publication number: 20100012917Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.Type: ApplicationFiled: May 31, 2006Publication date: January 21, 2010Inventors: Norikatsu Takaura, Yuichi Matsui, Motoyasu Terao, Yoshihisa Fujisaki, Nozomu Matsuzaki, Kenzo Kurotsuchi, Takahiro Morikawa
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Publication number: 20100010365Abstract: To increase intensity of the brain wave signal for detection. Provided is an apparatus for analyzing a brain wave which is installed on a vehicle comprising: a detection unit for detecting the brain wave signal, and separating and analyzing the detected brain wave signal; a discrimination unit for generating a control signal according to an intensity of the brain wave signal analyzed by the detection unit; a processing control unit for controlling subsequent processing according to a type of each of the plurality of control signals produced by the discrimination unit; at least one brain wave signal induction unit for generating a graphic inducing a predetermined type of the brain wave; and a display for displaying the generated graphic according to the received signal from the brain wave signal induction unit.Type: ApplicationFiled: May 5, 2009Publication date: January 14, 2010Inventors: Motoyasu Terao, Shigeru Oho, Yoshitaka Sasago
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Patent number: 7638786Abstract: The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.Type: GrantFiled: November 15, 2005Date of Patent: December 29, 2009Assignee: Renesas Technology Corp.Inventors: Yuichi Matsui, Motoyasu Terao, Norikatsu Takaura, Takahiro Morikawa, Naoki Yamamoto
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Publication number: 20090302293Abstract: On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.Type: ApplicationFiled: November 14, 2006Publication date: December 10, 2009Inventors: Takahiro Morikawa, Motoyasu Terao, Norikatsu Takaura, Kenzo Kurotsuchi
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Publication number: 20090262574Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: ApplicationFiled: April 21, 2009Publication date: October 22, 2009Inventors: Satoru HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Publication number: 20090250680Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.Type: ApplicationFiled: June 18, 2009Publication date: October 8, 2009Applicants: HITACHI, LTD., HITACHI ULSI SYSTEMS CO., LTD.Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Motoyasu Terao, Kenzo Kurotsuchi, Tsuyoshi Yamauchi
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Publication number: 20090242868Abstract: A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change of resistance of the solid electrolyte layer, the solid electrolyte layer includes a composition, for example, of Cu—Ta—S and an ion supply layer in adjacent or close therewith as Cu—Ta—O, in which ions supplied from the ion supply layer form a conduction path in the solid electrolyte layer thereby making it possible to store information by the level of the resistance and applying the electric pulse to change the resistance, in which the ion supply layer includes crystals having, for example, a compositional ratio of: Cu—Ta—O=1:2:6 and rewriting operation can be performed stably.Type: ApplicationFiled: February 12, 2009Publication date: October 1, 2009Inventors: Kenzo KUROTSUCHI, Motoyasu TERAO, Norikatsu TAKAURA, Yoshihisa FUJISAKI, Kazuo ONO, Yoshitaka SASAGO
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Publication number: 20090189137Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.Type: ApplicationFiled: January 29, 2009Publication date: July 30, 2009Inventors: Masaharu Kinoshita, Motoyasu Terao, Hideyuki Matsuoka, Yoshitaka Sasago, Yoshinobu Kimura, Akio Shima, Mitsuharu Tai, Norikatsu Takaura