Abstract: Provided is a hydrogen reformer using exhaust gas, comprising: a catalytic reaction unit which generates a reforming gas containing hydrogen when exhaust gas generated in an engine and fuel are supplied thereto; and a heat exchange chamber which is mounted on an outer surface of the catalytic reaction unit and exchanges heat between the exhaust gas and the catalytic reaction unit to supply heat that is required for an endothermic reaction of the catalytic reaction unit, wherein heat of the exhaust gas is used for the endothermic reaction of a catalyst, such that a separate heat source for the endothermic reaction is unnecessary.

Abstract: A semiconductor device in which a threshold voltage is adjusted by a simplified process and current characteristics are improved, a method for fabricating the semiconductor device, and a layout design method for the semiconductor device. The semiconductor device may include a device isolation layer defining an active region in a substrate, a gate electrode extending in a first direction on the active region, a high-concentration impurity region in the active region on a side of the gate electrode and extending in the first direction, and a low-concentration impurity region at least partly surrounding the high-concentration impurity region. The active region may include a plurality of connecting sections below the gate electrode that protrude from the low-concentration impurity region and extend in a second direction that intersects the first direction. The device isolation layer may include a plurality of separating sections that separate the connecting sections from each other.

Abstract: Provided is a metal catalyst support including: a case having a space through which exhaust gas passes; and flat plates and corrugated plates which are alternately stacked in the case and coated with a catalyst, wherein the corrugated plates are formed such that a first corrugated plate and a second corrugated plate are disposed with the flat plate therebetween, the first corrugated plate and the second corrugated plate are disposed such that a first corrugated portion and a second corrugated portion are alternately and repeatedly formed, and the vertex of the first corrugated portion and the vertex of the second corrugated portion face and coincide with each other, to thereby minimize deformation during thermal expansion due to external impact, vibration and temperature change.

Abstract: A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.

Abstract: A semiconductor chip includes a substrate including a circuit area having a rectangular shape and a peripheral area surrounding the circuit area, a key area being overlapping a part of the circuit area and a part of the peripheral area, a plurality of drive circuit cells in the circuit area, and a conductive reference line on the peripheral area and extending in a first direction parallel to a first edge among four edges of the rectangular shape of the circuit area.

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a device isolation film on the substrate. An active region of the substrate is defined by the device isolation film on the substrate and has a first width in a horizontal direction. A gate electrode is on the active region and has a second width equal to or less than the first width of the active region in the horizontal direction. The integrated circuit device includes an insulating spacer over the device isolation film and the active region.

Abstract: A display drive chip includes an electrostatic discharge (ESD) protection circuit unit configured to protect a circuit from ESD, an output including output pins for ouputting an output signal from a circuit disposed in an electric circuit region located in a central part of the display drive chip, a main voltage metal line electrically connecting the ESD protection circuit unit and the output to each other in the electric circuit region, an auxiliary voltage metal line that is connected to the ESD protection circuit unit and is disposed in a region of the chip outside the perimeter of the electric circuit region, and connection metal lines electrically connect the auxiliary voltage metal line and the output pins to each other.

Abstract: Provided is a catalyst carrier module for a large-capacity catalyst reactor, which can be assembled in a large-capacity structure by laminating a flat plate and a wave plate to be fixed in a can without brazing the flat plate and the wave plate constituting a cell forming body, for use in a catalytic reactor requiring a large-capacity exhaust gas treatment. The catalyst carrier module (or block) includes: a can of a rectangular tube shape having an inlet and an outlet; at least one cell forming body in which a plurality of hollow cells are formed by alternately laminating a wave plate and a flat plate which are coated with a catalyst on a surface thereof and inserted into the can; and a fixing unit installed at the inlet and the outlet of the can to prevent the at least one cell forming body from detaching from the can.

Abstract: An analogue semiconductor device and a semiconductor IC device including the same include a substrate having a transistor, a MIM capacitor electrically separated from the transistor on the substrate and having a lower electrode, a dielectric layer and an upper electrode, interlayer insulation covering the transistor and the MIM capacitor and a BEOL resistor connected to the upper electrode and equipotential with the lower electrode. The BEOL resistor has a relatively large and easy-variable resistance with minimized parasitic capacitance between the resistor and the lower electrode of the MIM capacitor.

Abstract: A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a semiconductor package and a display apparatus which include the semiconductor chip are described. The semiconductor chip includes a circuit region disposed in a central part of a rectangle that is elongated in a first direction. The circuit region includes a plurality of driving circuit cells disposed at predetermined intervals in the first direction. A plurality of electrode pads is disposed around the circuit region, and a process pattern is disposed at at least one of the four sides of the rectangle.

Abstract: A display apparatus includes a plurality of pixels arranged in columns and rows in a display area, a data line extending in a first direction and connected with pixels of a k-th column (‘k’ is a natural number) and a (k+1)-th column, a gate line extending in a second direction crossing the first direction and connected with ones of the pixels, a gate signal line extending in the first direction and connected with the gate line, and a gate driver in a first peripheral area adjacent to a first longer side of the display area and having a first width, and configured to apply a gate signal to the gate line.

Abstract: A fine pattern structure includes a lower hard mask layer on a pattern formation layer having a first region and a second region, first upper hard mask patterns disposed on the lower hard mask layer in the first region to expose portions of the lower hard mask layer, a second upper hard mask pattern covering the lower hard mask layer in the second region, guide patterns on the first and second upper hard mask patterns, neutralization patterns on the exposed portions of the lower hard mask layer in the first region, a first block co-polymer layer covering the guide patterns in the first region and the neutralization patterns, and a second block co-polymer layer covering the guide pattern in the second region.

Abstract: A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.

Abstract: The present invention relates to a thin film deposition apparatus, which includes: a deposition chamber supporting a substrate therein; a plurality of crucibles keeping a deposition material to be deposited on the substrate; a distribution conduits coupled to the crucibles, respectively, and arranged in a line to spray an evaporated deposition material through a plurality of nozzles; a separator disposed between the distribution conduits for uniformity of a thin film deposited on the substrate and limiting a spray range of the evaporated deposition material; distribution conduit heaters independently installed and facing outer sides of the distribution conduits to heat the distribution conduits; crucible heaters heating the crucibles to evaporate the deposition material; and a top plate having an exit port corresponding to the nozzles and disposed over the distribution conduits.

Abstract: An analogue semiconductor device and a semiconductor IC device including the same include a substrate having a transistor, a MIM capacitor electrically separated from the transistor on the substrate and having a lower electrode, a dielectric layer and an upper electrode, interlayer insulation covering the transistor and the MIM capacitor and a BEOL resistor connected to the upper electrode and equipotential with the lower electrode. The BEOL resistor has a relatively large and easy-variable resistance with minimized parasitic capacitance between the resistor and the lower electrode of the MIM capacitor.

Abstract: The present invention relates to a thin film deposition apparatus, which includes: a deposition chamber supporting a substrate therein; a plurality of crucibles keeping a deposition material to be deposited on the substrate; a distribution conduit having a plurality of coupling holes axially arranged to communicate with the crucibles, and spraying the deposition material evaporated from the crucibles through a plurality of nozzles formed through a top thereof; distribution conduit heaters independently installed and facing an outer side of the distribution conduit to heat the distribution conduit; crucible heaters heating the crucibles to evaporate the deposition material; and a top plate having an exit port corresponding to the nozzles and disposed over the distribution conduit. Accordingly, it is possible to reduce the height of the chamber by decreasing the height of the crucibles and to perform symmetric or asymmetric deposition by independently performing left/right deposition on a substrate.

Abstract: A display drive chip includes an electrostatic discharge (ESD) protection circuit unit configured to protect a circuit from ESD, an output including output pins for ouputting an output signal from a circuit disposed in an electric circuit region located in a central part of the display drive chip, a main voltage metal line electrically connecting the ESD protection circuit unit and the output to each other in the electric circuit region, an auxiliary voltage metal line that is connected to the ESD protection circuit unit and is disposed in a region of the chip outside the perimeter of the electric circuit region, and connection metal lines electrically connect the auxiliary voltage metal line and the output pins to each other.

Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.

Abstract: A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a semiconductor package and a display apparatus which include the semiconductor chip are described. The semiconductor chip includes a circuit region disposed in a central part of a rectangle that is elongated in a first direction. The circuit region includes a plurality of driving circuit cells disposed at predetermined intervals in the first direction. A plurality of electrode pads is disposed around the circuit region, and a process pattern is disposed at at least one of the four sides of the rectangle.

Abstract: A method of driving a light-source module includes adjusting a frequency of a boosting switching signal based on a dimming signal which controls luminance of a light-emitting diode (“LED”) string of the light-source module, where the LED string comprises a plurality of LEDs connected to each other in series, and controlling a main transistor in response to the boosting switching signal to transfer a driving voltage to the LED string.