Patents by Inventor Myoung-soo Kim

Myoung-soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9578753
    Abstract: A method for manufacturing a display device includes: connecting a first printed circuit board and a second printed circuit board with a first connecting film, the first printed circuit board and the second printed circuit board configured to apply a driving signal to a display panel; attaching a fixing member to the first printed circuit board and the second printed circuit board, such that the first connecting film extends away from the display panel and the first printed circuit board is spaced apart from the display panel; attaching the second printed circuit board to the display panel with second connecting films; removing the fixing member; and attaching the first printed circuit board to the display panel.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Dae Bae, Myoung-Soo Kim
  • Patent number: 9548021
    Abstract: A method of driving a light-source module includes adjusting a frequency of a boosting switching signal based on a dimming signal which controls luminance of a light-emitting diode (“LED”) string of the light-source module, where the LED string comprises a plurality of LEDs connected to each other in series, and controlling a main transistor in response to the boosting switching signal to transfer a driving voltage to the LED string.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 17, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Wan Kim, Min-Soo Choi, Gwang-Teak Lee, Tae-Gon Im, Myoung-Soo Kim, Hwan-Woong Lee, Seung-Young Choi
  • Patent number: 9520359
    Abstract: A semiconductor device, which may be included in a display driver integrated circuit (IC) and a display device, includes a first interconnection and a second interconnection extending on a substrate and separate from each other, a third interconnection extending at a first level that is higher than a level at which the first interconnection and the second interconnection are disposed, and a fourth interconnection extending at a second level that is higher than the first level. A first contact plug is configured to connect the first interconnection and the third interconnection to each other. A stacked contact plug includes a second contact plug and a third contact plug, wherein the second contact plug is connected to the second interconnection, and the third contact plug is connected to the second contact plug and the fourth interconnection.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung-Soo Kim
  • Patent number: 9418623
    Abstract: A backlight unit includes a power converter configured to generate a light source driving voltage in response to a voltage control signal, a plurality of light emitting diode strings, where each of the light emitting diode strings receives the light source driving voltage through a first terminal thereof, a plurality of transistors corresponding to the light emitting diode strings, where each of the transistors includes: a first electrode connected to a second terminal of a corresponding light emitting diode string thereof; a second electrode; and a control electrode, and a controller connected to the control electrode and the second electrode, where the controller outputs a plurality of current control signals to control electrodes of the transistors and generate the voltage control signal, where the controller generates an over-current detection signal when any one of the current control signals has a pulse width less than a predetermined reference width.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Taegon Im, Myoung-Soo Kim, Hwanwoong Lee, Min-Soo Choi, Eun Chul Shin, Dae-Sik Lee
  • Publication number: 20160133214
    Abstract: A display apparatus includes a plurality of pixels arranged in columns and rows in a display area, a data line extending in a first direction and connected with pixels of a k-th column (‘k’ is a natural number) and a (k+1)-th column, a gate line extending in a second direction crossing the first direction and connected with ones of the pixels, a gate signal line extending in the first direction and connected with the gate line, and a gate driver in a first peripheral area adjacent to a first longer side of the display area and having a first width, and configured to apply a gate signal to the gate line.
    Type: Application
    Filed: May 1, 2015
    Publication date: May 12, 2016
    Inventors: Ho-Kyoon Kwon, Myoung-Soo Kim, Sang-Ik Lee, Kyoung-Ho Lim, Kwang-Chul Jung, Jun-Ki Jeong, Ki-Seok Cha, Joon-Chul Goh, Bong-Hyun You
  • Publication number: 20160125833
    Abstract: A semiconductor device, which may be included in a display driver integrated circuit (IC) and a display device, includes a first interconnection and a second interconnection extending on a substrate and separate from each other, a third interconnection extending at a first level that is higher than a level at which the first interconnection and the second interconnection are disposed, and a fourth interconnection extending at a second level that is higher than the first level. A first contact plug is configured to connect the first interconnection and the third interconnection to each other. A stacked contact plug includes a second contact plug and a third contact plug, wherein the second contact plug is connected to the second interconnection, and the third contact plug is connected to the second contact plug and the fourth interconnection.
    Type: Application
    Filed: July 31, 2015
    Publication date: May 5, 2016
    Inventor: MYOUNG-SOO KIM
  • Publication number: 20160049408
    Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.
    Type: Application
    Filed: October 28, 2015
    Publication date: February 18, 2016
    Inventors: Jin Ki JUNG, Myoung Soo KIM
  • Patent number: 9257281
    Abstract: A method of fabricating a pattern comprising sequentially forming a pattern formation layer and a neutral layer on over a substrate having in a first regions and a second regions, forming guide patterns on first portions of over the neutral layer in the second regions, forming a first block copolymer layers on over second portions of the neutral layer in the first regions, phase-separating the tint block copolymer layers such that each of the first block copolymer layers includes to form first polymer blocks having a first phase and first polymer blocks having a second phase, removing the guide patterns to form openings that expose the first portions of the neutral layer in the second region, forming a second block copolymer layer on over the phase-separated first block copolymer layers and in the openings, phase-separating the second block copolymer layer into to form second polymer blocks having the first phase and second polymer blocks having the second phase removing the second polymer blocks having the s
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: February 9, 2016
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim
  • Patent number: 9202775
    Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: December 1, 2015
    Assignee: SK HYNIX INC.
    Inventors: Jin Ki Jung, Myoung Soo Kim
  • Patent number: 9190274
    Abstract: Methods of forming fine patterns are provided. The method includes reinforcing a hydrophobic property of a hard mask layer using a surface treatment process to form a neutral layer, forming a block co-polymer layer on the neutral layer, and phase-separating the block co-polymer layer into first domains and second domains.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 17, 2015
    Assignee: SK HYNIX INC.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Ki Lyoung Lee, Hyun Kyung Shim
  • Patent number: 9165769
    Abstract: A fine pattern structure includes a layer having or including alternating protrusion portions and recess portions, polymer patterns disposed in recess regions formed by the recess portions, brush patterns disposed on top surfaces of the protrusion portions, and a block co-polymer layer including first polymer block patterns formed on the brush patterns and second polymer block patterns formed on the polymer patterns.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 20, 2015
    Assignee: SK hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Jung Gun Heo
  • Publication number: 20150279661
    Abstract: A fine pattern structure includes a layer having or including alternating protrusion portions and recess portions, polymer patterns disposed in recess regions formed by the recess portions, brush patterns disposed on top surfaces of the protrusion portions, and a block co-polymer layer including first polymer block patterns formed on the brush patterns and second polymer block patterns formed on the polymer patterns.
    Type: Application
    Filed: June 12, 2015
    Publication date: October 1, 2015
    Inventors: Keun Do BAN, Cheol Kyu BOK, Myoung Soo KIM, Jung Gun HEO
  • Publication number: 20150273790
    Abstract: A fine pattern structure includes a lower hard mask layer on a pattern formation layer having a first region and a second region, first upper hard mask patterns disposed on the lower hard mask layer in the first region to expose portions of the lower hard mask layer, a second upper hard mask pattern covering the lower hard mask layer in the second region, guide patterns on the first and second upper hard mask patterns, neutralization patterns on the exposed portions of the lower hard mask layer in the first region, a first block co-polymer layer covering the guide patterns in the first region and the neutralization patterns, and a second block co-polymer layer covering the guide pattern in the second region.
    Type: Application
    Filed: June 12, 2015
    Publication date: October 1, 2015
    Inventors: Jung Hyung LEE, Cheol Kyu BOK, Keun Do BAN, Myoung Soo KIM, Ki Lyoung LEE
  • Patent number: 9147595
    Abstract: A semiconductor device includes a substrate and a plurality of active pillars disposed on the substrate and spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region stacked on the buried metal silicide pattern, and the active region includes impurity junction regions.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 29, 2015
    Assignee: SK HYNIX INC.
    Inventors: Sang Do Lee, Hae Jung Lee, Myoung Soo Kim, Sang Kil Kang
  • Publication number: 20150228475
    Abstract: A method of fabricating a pattern comprising sequentially forming a pattern formation layer and a neutral layer on over a substrate having in a first regions and a second regions, forming guide patterns on first portions of over the neutral layer in the second regions, forming a first block copolymer layers on over second portions of the neutral layer in the first regions, phase-separating the tint block copolymer layers such that each of the first block copolymer layers includes to form first polymer blocks having a first phase and first polymer blocks having a second phase, removing the guide patterns to form openings that expose the first portions of the neutral layer in the second region, forming a second block copolymer layer on over the phase-separated first block copolymer layers and in the openings, phase-separating the second block copolymer layer into to form second polymer blocks having the first phase and second polymer blocks having the second phase removing the second polymer blocks having the s
    Type: Application
    Filed: July 8, 2014
    Publication date: August 13, 2015
    Inventors: Keun Do BAN, Cheol Kyu BOK, Myoung Soo KIM
  • Publication number: 20150230347
    Abstract: A method for manufacturing a display device includes: connecting a first printed circuit board and a second printed circuit board with a first connecting film, the first printed circuit board and the second printed circuit board configured to apply a driving signal to a display panel; attaching a fixing member to the first printed circuit board and the second printed circuit board, such that the first connecting film extends away from the display panel and the first printed circuit board is spaced apart from the display panel; attaching the second printed circuit board to the display panel with second connecting films; removing the fixing member; and attaching the first printed circuit board to the display panel.
    Type: Application
    Filed: August 19, 2014
    Publication date: August 13, 2015
    Inventors: Sung-Dae BAE, Myoung-Soo KIM
  • Patent number: 9086632
    Abstract: A method for fine pattern structures includes forming a pattern formation layer over a first region and a second region of a substrate, forming a first block co-polymer layer in the first region, forming a second block co-polymer layer in the second region, etching the first and second block co-polymer layers, and forming the fine pattern structure in the pattern formation layer in the first region without forming a pattern in the pattern formation layer in the second region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 21, 2015
    Assignee: SK HYNIX INC.
    Inventors: Jung Hyung Lee, Cheol Kyu Bok, Keun Do Ban, Myoung Soo Kim, Ki Lyoung Lee
  • Patent number: D753201
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: April 5, 2016
    Assignee: TaeguTec Ltd.
    Inventor: Myoung Soo Kim
  • Patent number: D753738
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: April 12, 2016
    Assignee: TaeguTec Ltd.
    Inventor: Myoung Soo Kim
  • Patent number: D771165
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: November 8, 2016
    Assignee: TaeguTec Ltd.
    Inventor: Myoung Soo Kim