Patents by Inventor Nai-Han Cheng
Nai-Han Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200152495Abstract: The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a warpage measurement module configured to determine one or more substrate warpage parameters of a substrate. The substrate includes a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate. A metrology module is located physically downstream of the warpage measurement module and has an optical element configured to measure one or more dimensions of the substrate. The metrology module is configured to place the optical element at a plurality of different initial positions, which are directly over a plurality of different locations on the substrate, based upon the one or more substrate warpage parameters. A substrate transport system is configured to transfer the substrate from a first position within the warpage measurement module to a non-overlapping second position within the metrology module.Type: ApplicationFiled: January 7, 2020Publication date: May 14, 2020Inventors: Nai-Han Cheng, Chi-Ming Yang
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Publication number: 20200098544Abstract: The present disclosure describes an ion implantation system that includes a bushing designed to reduce the accumulation of IMP by-produces on the bushing's inner surfaces. The ion implantation system can include a chamber, an ion source configured to generate an ion beam, and a bushing coupling the ion source and the chamber. The bushing can include (i) a tubular body having an inner surface, a first end, and a second end and (ii) multiple angled trenches disposed within the inner surface of the tubular body, where each of the multiple angled trenches extends towards the second end of the tubular body.Type: ApplicationFiled: May 10, 2019Publication date: March 26, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Chieh MENG, Chui-Ya Peng, Nai-Han CHENG
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Patent number: 10541164Abstract: The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a substrate warpage measurement module configured to determine one or more substrate warpage parameters of a substrate by taking a plurality of separate measurements at a plurality of different positions over a substrate. The substrate has a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate and a conductive bump disposed over the dielectric structure and configured to be coupled to an additional substrate of a multi-dimensional chip. A substrate metrology module has an optical component and is configured to measure one or more dimensions of the conductive bump. A position control element is configured to move the optical component. A feed-forward path is coupled between an output of the substrate warpage measurement module and an input of the position control element.Type: GrantFiled: December 28, 2018Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Han Cheng, Chi-Ming Yang
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Publication number: 20190162676Abstract: In an embodiment, a system includes: a broadband light source; a wafer with a first side facing the broadband light source; a first light sensor configured to detect reflected light from the broadband light source emanating from the first side; a second light sensor configured to detect emergent light emanating from a second side of the wafer opposite the first side, wherein the emergent light originates from the broadband light source; and a detector module configured to analyze the reflected light and the emergent light to identify wafer defects.Type: ApplicationFiled: February 21, 2018Publication date: May 30, 2019Inventors: Nai-Han CHENG, Hsing-Piao HSU
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Publication number: 20190139800Abstract: The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a substrate warpage measurement module configured to determine one or more substrate warpage parameters of a substrate by taking a plurality of separate measurements at a plurality of different positions over a substrate. The substrate has a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate and a conductive bump disposed over the dielectric structure and configured to be coupled to an additional substrate of a multi-dimensional chip. A substrate metrology module has an optical component and is configured to measure one or more dimensions of the conductive bump. A position control element is configured to move the optical component. A feed-forward path is coupled between an output of the substrate warpage measurement module and an input of the position control element.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Nai-Han Cheng, Chi-Ming Yang
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Patent number: 10269530Abstract: An apparatus includes an ionization chamber and an electron source device at least partially disposed inside the ionization chamber. The ionization chamber is configured to receive at least one chemical and provide plasma having ionized chemicals. The electron source device includes at least one filament configured to generate electrons, and a cathode configured to emit secondary electrons from the front surface when the electrons from the at least one filament hit the back surface of the cathode. The front surface of the cathode is shaped convex facing inside the ionization chamber.Type: GrantFiled: January 31, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsing-Piao Hsu, Nai-Han Cheng, Shih-Fang Chen
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Patent number: 10181415Abstract: In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One or more substrate warpage parameters of the substrate are measured and an initial position of a lens within a substrate metrology module is calculated based upon the one or more substrate warpage parameters. The lens is then moved to the initial position, and a height and a width of the bump are measured using the substrate metrology module after moving the lens to the initial position.Type: GrantFiled: December 5, 2017Date of Patent: January 15, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Han Cheng, Chi-Ming Yang
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Publication number: 20180166291Abstract: In some embodiments of the present disclosure, a method of treating an atom on a substrate includes an operation of ionizing an etchant and the ionized etchant is a positively charged. The method includes an operation of attaching the ionized etchant on the atom. The method also includes an operation of bonding the atom with the etchant to from a compound. The method further includes sputtering the substrate with a charged particle and an operation of applying a bias on the water.Type: ApplicationFiled: February 9, 2018Publication date: June 14, 2018Inventors: NAI-HAN CHENG, CHI-MING YANG
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Publication number: 20180096872Abstract: In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One or more substrate warpage parameters of the substrate are measured and an initial position of a lens within a substrate metrology module is calculated based upon the one or more substrate warpage parameters. The lens is then moved to the initial position, and a height and a width of the bump are measured using the substrate metrology module after moving the lens to the initial position.Type: ApplicationFiled: December 5, 2017Publication date: April 5, 2018Inventors: Nai-Han Cheng, Chi-Ming Yang
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Patent number: 9929045Abstract: A defect inspection and repairing method is disclosed. The method includes: providing a wafer including a semiconductor chip disposed on a surface of the wafer; disposing a layer over the semiconductor chip; obtaining a scanned image of the disposed layer; performing an image analysis upon the scanned image to obtain a defect information; and generating a recipe of a beam according to the defect information, wherein the beam is configured to apply on the disposed layer. Associated system and non-transitory computer-readable medium are also disclosed.Type: GrantFiled: July 14, 2016Date of Patent: March 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Nai-Han Cheng, Chi-Ming Yang
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Patent number: 9892931Abstract: In some embodiments of the present disclosure, an apparatus includes an ionizer. The ionizer is configured to dispatch a reactive ion on a surface. The apparatus also has an implanter and the implanter has an outlet releasing an accelerated charged particle on the surface.Type: GrantFiled: October 14, 2013Date of Patent: February 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Nai-Han Cheng, Chi-Ming Yang
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Patent number: 9892954Abstract: A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to measure a thickness of a first layer on a back side of a wafer. The process chamber is configured to perform a treatment on a front side of the wafer. The front side is opposite the back side. The process chamber includes therein a multi-zone chuck. The multi-zone chuck is configured to support the back side of the wafer. The multi-zone chuck has a plurality of zones with controllable clamping forces for securing the wafer to the multi-zone chuck. The controller is coupled to the metrology chamber and the multi-zone chuck. The controller is configured to control the clamping forces in the corresponding zones in accordance with measured values of the thickness of the first layer in the corresponding zones.Type: GrantFiled: March 20, 2014Date of Patent: February 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nai-Han Cheng, Chi-Ming Yang, You-Hua Chou, Kuo-Sheng Chuang, Chin-Hsiang Lin
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Publication number: 20180019166Abstract: A defect inspection and repairing method is disclosed. The method includes: providing a wafer including a semiconductor chip disposed on a surface of the wafer; disposing a layer over the semiconductor chip; obtaining a scanned image of the disposed layer; performing an image analysis upon the scanned image to obtain a defect information; and generating a recipe of a beam according to the defect information, wherein the beam is configured to apply on the disposed layer. Associated system and non-transitory computer-readable medium are also disclosed.Type: ApplicationFiled: July 14, 2016Publication date: January 18, 2018Inventors: NAI-HAN CHENG, CHI-MING YANG
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Patent number: 9865429Abstract: The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.Type: GrantFiled: November 14, 2014Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hong Hwang, Chun-Lin Chang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9859139Abstract: The present disclosure relates to a method of bump metrology that relies upon advanced process control (APC) to provide substrate warpage parameters describing a warpage of a substrate to a bump metrology module to improve focus of the bump metrology module. In some embodiments, the method measures one or more substrate warpage parameters of a semiconductor substrate. An initial focal height of a lens of a bump metrology module is calculated based upon the measured substrate warpage parameters. The lens of the bump metrology module is then placed at the initial focal height, and height and critical dimensions of a plurality of bumps on the semiconductor substrate are subsequently measured using the lens. By providing the substrate warpage parameters to the bump metrology module, the bump metrology module can use real-time process control to account for wafer warpage, thereby improving throughput and yield.Type: GrantFiled: July 14, 2015Date of Patent: January 2, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Han Cheng, Chi-Ming Yang
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Patent number: 9805913Abstract: A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate.Type: GrantFiled: June 2, 2015Date of Patent: October 31, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hong Hwang, Chun-Lin Chang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Publication number: 20170018445Abstract: The present disclosure relates to a method of bump metrology that relies upon advanced process control (APC) to provide substrate warpage parameters describing a warpage of a substrate to a bump metrology module to improve focus of the bump metrology module. In some embodiments, the method measures one or more substrate warpage parameters of a semiconductor substrate. An initial focal height of a lens of a bump metrology module is calculated based upon the measured substrate warpage parameters. The lens of the bump metrology module is then placed at the initial focal height, and height and critical dimensions of a plurality of bumps on the semiconductor substrate are subsequently measured using the lens. By providing the substrate warpage parameters to the bump metrology module, the bump metrology module can use real-time process control to account for wafer warpage, thereby improving throughput and yield.Type: ApplicationFiled: July 14, 2015Publication date: January 19, 2017Inventors: Nai-Han Cheng, Chi-Ming Yang
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Patent number: 9449889Abstract: A method comprises placing a wafer and a ring-shaped beam profiler on a wafer holder, wherein the ring-shaped beam profiler is adjacent to the wafer, moving a first sensor and a second sensor simultaneously with the wafer holder, receiving a first sensed signal and a second sensed signal from the first sensor and the second sensor respectively and adjusting an ion beam generated by an ion beam generator based upon the first sensed signal and the second sensed signal.Type: GrantFiled: April 13, 2015Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Lin Chang, Chih-Hong Hwang, Nai-Han Cheng, Chi-Ming Yang, Chin-Hsiang Lin
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Patent number: 9315892Abstract: One or more techniques or systems for ion implantation are provided herein. A pressure control module is configured to maintain a substantially constant pressure within an ion implantation or process chamber. Pressure is maintained based on an attribute of an implant layer, pressure data, feedback, photo resist (PR) outgassing, a PR coating rate, a space charge effect associated with the implant layer, etc. By maintaining pressure within the process chamber, effects associated with PR outgassing are mitigated, thereby mitigating neutralization of ions. By maintaining charged ions, better control over implantation of the ions is achieved, thus allowing ions to be implanted at a desired depth.Type: GrantFiled: March 15, 2013Date of Patent: April 19, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Nai-Han Cheng, Chi-Ming Yang
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Patent number: 9239192Abstract: A method and apparatus for rapid thermal heat treatment of semiconductor and other substrates is provided. A number of heat lamps arranged in an array or other configuration produce light and heat radiation. The light and heat radiation is directed through a heat slot that forms a radiation beam of high intensity light and heat. The radiation beam is directed to a platen that includes multiple substrates. The apparatus and method include a controller that controls rotational and translational motion of the platen relative to the heat slot and also controls the power individually and collectively supplied to the heat lamps. A program is executed which maneuvers the platen such that all portions of all substrates receive the desired thermal treatment, i.e. attain a desired temperature for a desired time period.Type: GrantFiled: February 20, 2013Date of Patent: January 19, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Han Cheng, Chi-Ming Yang