Abstract: In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones.

Abstract: The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.

Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.

Abstract: A beam monitoring device, method, and system is disclosed. An exemplary beam monitoring device includes a one dimensional (1D) profiler. The 1D profiler includes a Faraday having an insulation material and a conductive material. The beam monitoring device further includes a two dimensional (2D) profiler. The 2D profiler includes a plurality of Faraday having an insulation material and a conductive material. The beam monitoring device further includes a control arm. The control arm is operable to facilitate movement of the beam monitoring device in a longitudinal direction and to facilitate rotation of the beam monitoring device about an axis.

Abstract: An multi-ion beam implantation apparatus and method are disclosed. An exemplary apparatus includes an ion beam source that emits at least two ion beams; an ion beam analyzer; and a multi-ion beam angle incidence control system. The ion beam analyzer and the multi-ion beam angle incidence control system are configured to direct the emitted at least two ion beams to a wafer.

Abstract: An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second sensor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second sensor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer.

Abstract: A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD.

Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.

Abstract: A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD.

Abstract: An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

Abstract: An apparatus for monitoring beam currents of an implanter is provided. The apparatus includes a beam-sensing unit for sensing the beam currents; a position-determining unit for determining scan positions; and a computing unit. The computing unit is configured to perform the functions of receiving the beam currents from the beam-sensing unit; receiving the scan positions from the position-determining unit; and determining a drift status of the implanter from the beam currents, wherein the computing unit is configured to receive the beam currents and the scan position periodically between a starting time and an ending time of a scan process of the implanter.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.

Abstract: A system for implantation dosage control. A first interface receives scan position information. A second interface receives beam current information specifying a first beam current value between scans and a plurality of second beam current values during one of the scans. A controller, determines a tolerance range according to the first beam current value, determines whether the second beam current values exceeds the tolerance range, and calculates number of the second beam current values exceeding the tolerance range.

Abstract: A system for implantation dosage control. A first interface receives scan position information. A second interface receives beam current information specifying a first beam current value between scans and a plurality of second beam current values during one of the scans. A controller, determines a tolerance range according to the first beam current value, determines whether the second beam current values exceeds the tolerance range, and calculates number of the second beam current values exceeding the tolerance range.