Abstract: A semiconductor device includes: a plurality of pixel units disposed in a matrix shape, each of the plurality of pixel units including: a first photoelectric conversion element for converting incident light of a first color into signal charges; a second photoelectric conversion element for converting incident light of a second color into signal charges; a third photoelectric conversion element for converting incident light of a third color into signal charges; and a detector circuit shared by the first to third photoelectric conversion elements for detecting the signal charges converted by each of the first to third photoelectric conversion elements, wherein the plurality of pixel units are pixel units adjacently disposing a row (column) juxtaposing the first photoelectric conversion element and detector circuit and a row (column) juxtaposing the second and third photoelectric conversion elements.

Abstract: An image sensor has a plurality of pixels each with a photoelectric conversion element and a detection transistor the threshold voltage of which fluctuates in accordance with electrical charge generated in the photoelectric conversion element. The image sensor includes a second conductivity type shield region and a first conductivity type photoelectric conversion region; a first conductivity type well region linked to the photoelectric conversion region; a ring-like gate electrode; a second conductivity type source region at the inside of the ring-like gate electrode; a second conductivity type drain region. The image sensor further includes a potential pocket region that is formed in the well region below the ring-like gate electrode and accumulates the electrical charge, wherein the width of the gate electrode is formed narrower in the part adjacent to the photoelectric conversion region than in other parts.

Abstract: A semiconductor device includes: a plurality of pixel units disposed in a matrix shape, each of the plurality of pixel units including: a first photoelectric conversion element for converting incident light of a first color into signal charges; a second photoelectric conversion element for converting incident light of a second color into signal charges; a third photoelectric conversion element for converting incident light of a third color into signal charges; and a detector circuit shared by the first to third photoelectric conversion elements for detecting the signal charges converted by each of the first to third photoelectric conversion elements, wherein the plurality of pixel units are pixel units adjacently disposing a row (column) juxtaposing the first photoelectric conversion element and detector circuit and a row (column) juxtaposing the second and third photoelectric conversion elements.

Abstract: A semiconductor device including a pixel region in which one or more pixels are formed and a DRAM cell region in which one or more DRAM cells for storing output signals from the pixels are formed, characterized in that the layers constituting the pixel region and the DRAM cell region are formed in the same semiconductor process.

Abstract: In an arrangement with four PDs (PD1 to PD4) aligned along the column direction sharing the signal voltage reading unit, respective elements are disposed in the order of: PD/FD1 and TG-Tr1, 2/PD2/SF-Tr and SL-Tr/PD3/FD2 and TG-Tr3, 4/PD4/RS-Tr.

Abstract: A semiconductor image sensor includes: a semiconductor substrate having a number of pixels disposed in a matrix shape, the semiconductor substrate comprising a first region including a charge accumulation region of a photodiode and a floating diffusion and a second region including transistors, each having a gate electrode and source/drain regions; a first silicon oxide film formed above the semiconductor substrate, covering the surface of the charge accumulation region in the first region and formed as side wall spacers on side of the gate electrode walls of at lease some transistors in the second region; and a silicon nitride film formed above the first silicon oxide film, covering the source/drain regions in the second region and having an opening at least in an area above the charge accumulation region in the first region. The semiconductor image sensor is provided which has a high sensitivity and can supply an output with small noises.

Abstract: In an arrangement with four PDs (PD1 to PD4) aligned along the column direction sharing the signal voltage reading unit, respective elements are disposed in the order of: PD/FD1 and TG-Tr1,2/PD2/SF-Tr and SL-Tr/PD3/FD2 and TG-Tr3, 4/PD4/RS-Tr.

Abstract: In the solid-state image sensor including 4-Tr-pixels, a source follower transistor SF-Tr, a rest transistor RST and a select transistor Select are made common between pixels Pn, Pn+1 adjacent in the column direction, and a transfer transistor TG1 and a transfer transistor TG2 are formed in region which respectively positioned on the same side with respect to the photodiode PD1 and the photodiode PD2, and the source follower transistor SF-Tr, the reset transistor RST and the select transistor Select made common are formed in regions positioned on the side in the row direction with respect to the photodiode PD1 and the photodiode PD2.

Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.

Abstract: A semiconductor imaging device includes a photodetection region formed of a diffusion region of a first conductivity type formed in an active region of a silicon substrate at a first side of a gate electrode such that a top part thereof is separated from a surface of the silicon substrate and such that an inner edge part invades underneath a channel region right underneath the gate electrode, a shielding layer formed of a second conductivity type at a surface of the silicon substrate at the first side of the gate electrode such that an inner edge part thereof is aligned with a sidewall surface of the gate electrode at the first side, a floating diffusion region formed in the active region at a second side of the gate electrode, and a channel region formed right underneath said gate electrode, wherein the channel region includes a first channel region part formed adjacent to the shielding layer and a second channel region part formed adjacent to the floating diffusion region, wherein the second channel region

Abstract: The present invention relates to a semiconductor device which comprises a plug layer which is embedded in a window penetrating an inter-layer insulation film, and flattened by using a chemical mechanical polishing, a titanium Ti film which is deposited to extend from the inter-layer insulation film to the plug layer, a titanium nitride TiN film which is deposited on the Ti film, a wiring layer which contains aluminum Al or copper Cu deposited on the TiN film, and an underlying film which is formed between the inter-layer insulation layer and the Ti film.

Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area.

Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.

Abstract: An image sensor in which a plurality of pixels having at least a photodiode, a reset transistor, and source follower transistor are formed, wherein each pixel comprises an electrical-charge transfer gate transistor between the photodiode and reset transistor, and a floating diffusion region constituting a node connecting the reset transistor and transfer gate transistor is connected to the gate of the source follower transistor. Further, a photodiode region is embedded below a well region in which the reset transistor and source follower transistor of each pixel are formed. In addition, the photo diode region is not formed below at least a partial region of the floating diffusion region.

Abstract: An image sensor is provided that can be made compact, low power consuming, and operative at high speed without degrading image quality and read-out speed. The image sensor includes a pixel cell having a photo diode 31 and a reset transistor 32 connected to a power supply, a detection transistor 33 for detecting the signal voltage of the photo diode 31, a selection transistor 34 for selecting the detection transistor 33 and reading the signal voltage therefrom; a peripheral circuit 12 having MOS transistors; and an input/output circuit 13 having MOS transistors. The gate dielectric films 60A of the reset transistor 32 and the detection transistor 33 are formed thicker than the gate dielectric film of the selection transistor 34.

Abstract: In the solid-state image sensor comprising 4-Tr-pixels, TG lines connecting the gate electrodes 28TG of the transfer transistors of the pixel units of the nth row, and select lines connecting the gate electrodes 28SEL of the select transistors of the pixel units of the n+1th row are formed of a common signal line, and the gate electrodes 28TG of the pixels of the nth row and the gate electrodes 28SEL of the pixel units of the n+1th row are formed in one continuous pattern of the same conducting layer. Whereby allowance can be given to layouts of the metal interconnection layers. Accordingly, the floating diffusions FD can be effectively shielded from light. Furthermore, allowance can be given to the area. Accordingly, the floating diffusions FD can have the area increased, whereby the junction leakage can be reduced.

Abstract: Provided is a photographing apparatus (CMOS image sensor) that enables enlarging the area that the PD occupies by making simple the layout within a pixel wherein a photo-electric conversion element and a plurality of CMOS transistors are laid out. The photographing apparatus is the one 1 wherein a photo-diode 11 constituting the photo-electric conversion element and a plurality of transistors 12, 13, 14, and 15 are laid out in parallel in the column arrangement direction of the pixels 10 that are arrayed in the form of a lattice. In the apparatus, further, the pixels 10 are each arrayed in the way of being shifted half the length of the pixel 10 in the column arrangement direction every row.

Abstract: A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.

Abstract: A CMOS image sensor with an effectively increased aperture ratio and moreover with improved optical sensitivity, and a method of manufacture of such a CMOS image sensor is provided a first aspect of the invention is an image sensor, has a pixel region 10 in which are formed a plurality of pixels each having at least a photodiode, a reset transistor, and a source-follower transistor; and a peripheral circuit region 12 in which are formed peripheral circuits which process read-out signals read out from the pixel region, a well region PW2 in the pixel region PW1 is formed to be more shallow than a well region in the peripheral circuit region. Also, reset transistors or source-follower transistors are formed in the shallow well region PW2 of the pixel region 10, and a photodiode region PHD2 is embedded below the transistor well region PW2.

Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.