Patents by Inventor Narumi Ohkawa

Narumi Ohkawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070252184
    Abstract: Disclosed is an imaging device including a photodiode and floating diffusion region formed to be spaced from each other on a surface layer of a pixel region of a silicon (semiconductor) substrate, and a transfer gate having one of a concave and convex portions toward the floating diffusion region, the transfer gate being formed above the silicon substrate between the photodiode and the floating diffusion region by interposing a gate insulating film therebetween.
    Type: Application
    Filed: June 25, 2007
    Publication date: November 1, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Narumi Ohkawa
  • Patent number: 7285838
    Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: October 23, 2007
    Assignee: Fujitsu Limited
    Inventors: Narumi Ohkawa, Masaya Katayama
  • Publication number: 20070158713
    Abstract: A CMOS imaging device formed of plural CMOS photosensors arranged in a row and column formation, wherein a first CMOS photosensor and a second CMOS photosensor adjacent with each other in a column direction are formed in a single, continuous device region defined on a semiconductor substrate by a device isolation region.
    Type: Application
    Filed: January 16, 2007
    Publication date: July 12, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Narumi Ohkawa
  • Patent number: 7242043
    Abstract: Disclosed is an imaging device including a photodiode and floating diffusion region formed to be spaced from each other on a surface layer of a pixel region of a silicon (semiconductor) substrate, and a transfer gate having one of a concave and convex portions toward the floating diffusion region, the transfer gate being formed above the silicon substrate between the photodiode and the floating diffusion region by interposing a gate insulating film therebetween.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: July 10, 2007
    Assignee: Fujitsu Limited
    Inventor: Narumi Ohkawa
  • Publication number: 20070145237
    Abstract: In an arrangement with four PDs (PD1 to PD4) aligned along the column direction sharing the signal voltage reading unit, respective elements are disposed in the order of: PD/FD1 and TG-Tr1,2/PD2/SF-Tr and SL-Tr/PD3/FD2 and TG-Tr3, 4/PD4/RS-Tr.
    Type: Application
    Filed: April 11, 2006
    Publication date: June 28, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Narumi Ohkawa
  • Publication number: 20070023800
    Abstract: A semiconductor imaging device includes a photodetection region formed of a diffusion region of a first conductivity type formed in an active region of a silicon substrate at a first side of a gate electrode such that a top part thereof is separated from a surface of the silicon substrate and such that an inner edge part invades underneath a channel region right underneath the gate electrode, a shielding layer formed of a second conductivity type at a surface of the silicon substrate at the first side of the gate electrode such that an inner edge part thereof is aligned with a sidewall surface of the gate electrode at the first side, a floating diffusion region formed in the active region at a second side of the gate electrode, and a channel region formed right underneath said gate electrode, wherein the channel region includes a first channel region part formed adjacent to the shielding layer and a second channel region part formed adjacent to the floating diffusion region, wherein the second channel region
    Type: Application
    Filed: October 17, 2005
    Publication date: February 1, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Narumi Ohkawa
  • Publication number: 20060275979
    Abstract: A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.
    Type: Application
    Filed: August 15, 2006
    Publication date: December 7, 2006
    Inventors: Maso Hayashi, Tadaaki Hayashi, Taiji Ema, Narumi Ohkawa
  • Patent number: 7119387
    Abstract: A solid-state image sensor comprises a semiconductor substrate of a first conductivity type having a color pixel region and a black pixel region; a first well of the first conductivity type formed in the color pixel region; a second well of the first conductivity type formed in the black pixel region; a third well of a second conductivity type formed, surrounding the second well and isolating the second well from the rest region of the semiconductor substrate; a color pixel formed in the first well in the color pixel region and including a first photodiode and a first read transistor for reading a signal generated by the first photodiode; and a black pixel formed in the second well in the black pixel region and including a second photodiode and a second read transistor for reading a signal generated by the second photodiode. The first well includes a first buried impurity doped layer of the first conductivity type formed in a bottom thereof in a region where the first read transistor is formed.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: October 10, 2006
    Assignee: Fujitsu Limited
    Inventor: Narumi Ohkawa
  • Patent number: 7118957
    Abstract: A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: October 10, 2006
    Assignee: Fujitsu Limited
    Inventors: Tadaaki Hayashi, legal representative, Taiji Ema, Narumi Ohkawa, Masao Hayashi, deceased
  • Publication number: 20060208285
    Abstract: An image sensor in which a plurality of pixels having at least a photodiode, a reset transistor, and source follower transistor are formed, wherein each pixel comprises an electrical-charge transfer gate transistor between the photodiode and reset transistor, and a floating diffusion region constituting a node connecting the reset transistor and transfer gate transistor is connected to the gate of the source follower transistor. Further, a photodiode region is embedded below a well region in which the reset transistor and source follower transistor of each pixel are formed. In addition, the photodiode region is not formed below at least a partial region of the floating diffusion region.
    Type: Application
    Filed: October 13, 2005
    Publication date: September 21, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Tadao Inoue, Katsuyoshi Yamamoto, Narumi Ohkawa
  • Publication number: 20060208289
    Abstract: A semiconductor image sensor includes: a semiconductor substrate having a number of pixels disposed in a matrix shape, the semiconductor substrate comprising a first region including a charge accumulation region of a photodiode and a floating diffusion and a second region including transistors, each having a gate electrode and source/drain regions; a first silicon oxide film formed above the semiconductor substrate, covering the surface of the charge accumulation region in the first region and formed as side wall spacers on side of the gate electrode walls of at lease some transistors in the second region; and a silicon nitride film formed above the first silicon oxide film, covering the source/drain regions in the second region and having an opening at least in an area above the charge accumulation region in the first region. The semiconductor image sensor is provided which has a high sensitivity and can supply an output with small noises.
    Type: Application
    Filed: September 1, 2005
    Publication date: September 21, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Narumi Ohkawa, Shigetoshi Takeda, Yukihiro Ishihara, Kazuki Hayashi, Nobuhisa Naori, Masahiro Chijiiwa
  • Publication number: 20060145286
    Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.
    Type: Application
    Filed: April 29, 2005
    Publication date: July 6, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Narumi Ohkawa, Masaya Katayama
  • Publication number: 20060011952
    Abstract: A solid-state image sensor comprises a semiconductor substrate of a first conductivity type having a color pixel region and a black pixel region; a first well of the first conductivity type formed in the color pixel region; a second well of the first conductivity type formed in the black pixel region; a third well of a second conductivity type formed, surrounding the second well and isolating the second well from the rest region of the semiconductor substrate; a color pixel formed in the first well in the color pixel region and including a first photodiode and a first read transistor for reading a signal generated by the first photodiode; and a black pixel formed in the second well in the black pixel region and including a second photodiode and a second read transistor for reading a signal generated by the second photodiode. The first well includes a first buried impurity doped layer of the first conductivity type formed in a bottom thereof in a region where the first read transistor is formed.
    Type: Application
    Filed: November 22, 2004
    Publication date: January 19, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Narumi Ohkawa
  • Patent number: 6987041
    Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: January 17, 2006
    Assignee: Fujitsu Limited
    Inventor: Narumi Ohkawa
  • Publication number: 20050285165
    Abstract: An image sensor has a plurality of pixels each with a photoelectric conversion element and a detection transistor the threshold voltage of which fluctuates in accordance with electrical charge generated in the photoelectric conversion element. The image sensor includes a second conductivity type shield region and a first conductivity type photoelectric conversion region; a first conductivity type well region linked to the photoelectric conversion region; a ring-like gate electrode; a second conductivity type source region at the inside of the ring-like gate electrode; a second conductivity type drain region. The image sensor further includes a potential pocket region that is formed in the well region below the ring-like gate electrode and accumulates the electrical charge, wherein the width of the gate electrode is formed narrower in the part adjacent to the photoelectric conversion region than in other parts.
    Type: Application
    Filed: March 25, 2005
    Publication date: December 29, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Narumi Ohkawa, Masayoshi Asano, Toshio Nomura
  • Publication number: 20050255644
    Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area.
    Type: Application
    Filed: July 22, 2005
    Publication date: November 17, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Narumi Ohkawa
  • Publication number: 20050242402
    Abstract: The present invention relates to a semiconductor device which comprises a plug layer which is embedded in a window penetrating an inter-layer insulation film, and flattened by using a chemical mechanical polishing, a titanium Ti film which is deposited to extend from the inter-layer insulation film to the plug layer, a titanium nitride TiN film which is deposited on the Ti film, a wiring layer which contains aluminium Al or copper Cu deposited on the TiN film, and an underlying film which is formed between the inter-layer insulation layer and the Ti film.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 3, 2005
    Inventor: Narumi Ohkawa
  • Publication number: 20050237405
    Abstract: In the solid-state image sensor including 4-Tr-pixels, a source follower transistor SF-Tr, a rest transistor RST and a select transistor Select are made common between pixels Pn, Pn+1 adjacent in the column direction, and a transfer transistor TG1 and a transfer transistor TG2 are formed in region which respectively positioned on the same side with respect to the photodiode PD1 and the photodiode PD2, and the source follower transistor SF-Tr, the reset transistor RST and the select transistor Select made common are formed in regions positioned on the side in the row direction with respect to the photodiode PD1 and the photodiode PD2.
    Type: Application
    Filed: August 25, 2004
    Publication date: October 27, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Narumi Ohkawa
  • Publication number: 20050224853
    Abstract: A semiconductor device including a pixel region in which one or more pixels are formed and a DRAM cell region in which one or more DRAM cells for storing output signals from the pixels are formed, characterized in that the layers constituting the pixel region and the DRAM cell region are formed in the same semiconductor process.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 13, 2005
    Inventor: Narumi Ohkawa
  • Patent number: 6930299
    Abstract: Pixels are disposed on a semiconductor substrate in a matrix shape. Each pixel includes a photodiode, a reset transistor, a source follower transistor and a select transistor. An active region in which the photodiode and transistors are disposed includes a first area in which the photodiode is disposed and a second area having an are elongated in a first direction. Each of the gate electrodes of the reset transistor, source follower transistor and select transistor crosses the area, elongated in the first direction, of the second area. An intra-pixel wiring line interconnects the drain region of the reset transistor and the gate electrode of the source follower transistor.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: August 16, 2005
    Assignee: Fujitsu Limited
    Inventor: Narumi Ohkawa