Abstract: An image sensor is provided that can be made compact, low power consuming, and operative at high speed without degrading image quality and read-out speed. The image sensor includes a pixel cell having a photo diode 31 and a reset transistor 32 connected to a power supply, a detection transistor 33 for detecting the signal voltage of the photo diode 31, a selection transistor 34 for selecting the detection transistor 33 and reading the signal voltage therefrom; a peripheral circuit 12 having MOS transistors; and an input/output circuit 13 having MOS transistors. The gate dielectric films 60A of the reset transistor 32 and the detection transistor 33 are formed thicker than the gate dielectric film of the selection transistor 34.

Abstract: A first layer of a first conductivity type is formed in a partial surface layer of an active region of a semiconductor substrate. A buried layer of a second conductivity type is disposed being partially superposed upon the first layer as viewed in plan. The buried layer is deeper than the first layer, and the upper surface of the buried layer is set to a position deeper than the bottom of a device isolation insulating region. A MISFET is formed in a region of the active region where the first layer is not formed. The bottoms of first and second impurity concentration regions corresponding to the source and drain of MISFET are disposed at a position shallower than the upper surface of the buried layer. A buried layer connection region of the second conductivity type electrically interconnects the first impurity diffusion region and the buried layer.

Abstract: Disclosed is an imaging device including a photodiode and floating diffusion region formed to be spaced from each other on a surface layer of a pixel region of a silicon (semiconductor) substrate, and a transfer gate having one of a concave and convex portions toward the floating diffusion region, the transfer gate being formed above the silicon substrate between the photodiode and the floating diffusion region by interposing a gate insulating film therebetween.

Abstract: Provided is a photographing apparatus (CMOS image sensor) that enables enlarging the area that the PD occupies by making simple the layout within a pixel wherein a photo-electric conversion element and a plurality of CMOS transistors are laid out. The photographing apparatus is the one 1 wherein a photo-diode 11 constituting the photo-electric conversion element and a plurality of transistors 12, 13, 14, and 15 are laid out in parallel in the column arrangement direction of the pixels 10 that are arrayed in the form of a lattice. In the apparatus, further, the pixels 10 are each arrayed in the way of being shifted half the length of the pixel 10 in the column arrangement direction every row.

Abstract: Pixels are disposed on a semiconductor substrate in a matrix shape. Each pixel includes a photodiode, a reset transistor, a source follower transistor and a select transistor. An active region in which the photodiode and transistors are disposed includes a first area in which the photodiode is disposed and a second area having an are elongated in a first direction. Each of the gate electrodes of the reset transistor, source follower transistor and select transistor crosses the area, elongated in the first direction, of the second area. An intra-pixel wiring line interconnects the drain region of the reset transistor and the gate electrode of the source follower transistor.

Abstract: In the solid-state image sensor comprising 4-Tr-pixels, TG lines connecting the gate electrodes 28TG of the transfer transistors of the pixel units of the nth row, and select lines connecting the gate electrodes 28SEL of the select transistors of the pixel units of the n+1th row are formed of a common signal line, and the gate electrodes 28TG of the pixels of the nth row and the gate electrodes 28SEL of the pixel units of the n+1th row are formed in one continuous pattern of the same conducting layer. Whereby allowance can be given to layouts of the metal interconnection layers. Accordingly, the floating diffusions FD can be effectively shielded from light. Furthermore, allowance can be given to the area. Accordingly, the floating diffusions FD can have the area increased, whereby the junction leakage can be reduced.

Abstract: A first layer of a first conductivity type is formed in a partial surface layer of an active region of a semiconductor substrate. A buried layer of a second conductivity type is disposed being partially superposed upon the first layer as viewed in plan. The buried layer is deeper than the first layer, and the upper surface of the buried layer is set to a position deeper than the bottom of a device isolation insulating region. A MISFET is formed in a region of the active region where the first layer is not formed. The bottoms of first and second impurity concentration regions corresponding to the source and drain of MISFET are disposed at a position shallower than the upper surface of the buried layer. A buried layer connection region of the second conductivity type electrically interconnects the first impurity diffusion region and the buried layer.

Abstract: A semiconductor device includes an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.

Abstract: A semiconductor device includes an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.

Abstract: First and second regions are defined in a principal surface of a semiconductor substrate. Two projected structures are disposed on the principal surface of the first region and spaced apart by a certain distance. The two projected structures run on a first active region in the first region and on an element isolation region around the first active region. A first silicide film is formed on the surface of a partial active region in the principal surface in the second region. A burying member covers the side walls of the two projected structures and buries a space between the two projected structures at least in the element isolation region. The burying member is not formed above the two projected structures. A metal silicide film is not formed on the surface of the first active region.

Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area.

Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned.

Abstract: A semiconductor device formed on a semiconductor substrate having a first region and a second region, comprising: a wiring layer made of a first conductive layer formed in the second region; a first insulating film formed on the wiring layer; a second insulating film formed on the first region and on the first insulating film; a first contact hole formed in the first region through the second insulating film, and reaching the surface of the first insulating film; a second contact hole having a larger diameter than the first contact hole formed in the second region through the second insulating film, and reaching the surface of the first insulating film; a plug made of a second conductive layer and filled in the first contact hole; a side spacer made of the second conductive layer and formed on the side wall of the second contact hole; and a third contact hole having a smaller diameter than the second contact hole, formed through the first insulating film positioned under the second contact hole, and reaching