Abstract: A decrease in output power due to a foreign matter present on a base at the time of forming a thin film solid electrolyte layer is limited, and an increase in yield even when an area of a fuel battery cell is increased, is obtained. The fuel battery cell has a membrane electrode assembly including a lower electrode layer, first and second solid electrolyte layers, and an upper electrode layer formed on a support substrate. An interface between the first and second solid electrolyte layers is flat as compared with an interface between the lower electrode layer and the solid electrolyte layer, and the second solid electrolyte layer has a thickness at which a leakage current between the first solid electrolyte layer and the second solid electrolyte layer is less than an allowable value even when an output voltage of the fuel battery cell is generated.

Abstract: A preferred aspect of the present invention is a fuel cell stack provided with a plurality of fuel cells each including a solid electrolyte layer and first and second electrode layers formed across the solid electrolyte layer. The fuel cells are stacked with the first or second electrode layers of adjacent cells facing each other. A common flow path for supplying a first gas to both of the first electrode layers facing each other is formed in an area where the first electrode layers face each other. A common flow path for supplying a second gas to both of the second electrode layers facing each other is formed in an area where the second electrode layers face each other. A connection electrode is formed at the end of the fuel cell. At least some of the stacked cells are connected in series via the connection electrode.

Abstract: An object of the present invention is to provide a fuel cell that obtains high output density and prevents stress application to the cell during stack assembling and breakage. The fuel cell is equipped with a unit cell including a structure in which an electrolyte layer is sandwiched between an anode electrode layer and a cathode electrode layer. The unit cell is disposed between a first member and a second member. An intermediate substrate is disposed between the first member and the second member. The unit cell is supported at the outer peripheral portion thereof by the intermediate substrate. The width of the electrolyte layer is the maximum width or less of a hollow portion formed between at least one of the first member and the second member and the unit cell.

Abstract: A fuel cell 1 includes a silicon substrate 2, a porous support material layer 5, a plurality of holes 60 or columns 40, and a stacked body. The stacked body includes an upper electrode layer 10, a solid electrolyte layer 100 and a lower electrode layer 20. The upper electrode layer 10 is also formed on a surface parallel to a main surface of the silicon substrate 2 in a manner of being continuous to the upper electrode layer 10 formed in the plurality of holes 60 or columns 40, or the lower electrode layer 20 is also formed on a surface parallel to the main surface of the silicon substrate 2 in a manner of being continuous to the lower electrode layer 20 formed in the plurality of holes 60 or columns 40. The stacked body is supported by the porous support material layer 5 in at least upper end portions and lower end portions of the plurality of holes 60 or columns 40.

Abstract: An object of the present invention is to provide a fuel cell that maintains electric generation efficiency of the fuel cell and that has high reliability in which an electrolyte film is not easily damaged. The fuel cell according to the present invention includes a stress adjusting layer covering an opening above a support substrate, and the stress adjusting layer has tensile stress with respect to the support substrate and has a columnar crystal structure in which a grain boundary extends along a direction parallel to a film thickness direction (see FIG. 2).

Abstract: An object of the present invention is to provide a fuel battery cell of a high power generation output by increasing an area of an effective power generation region contributing to power generation while ensuring mechanical strength of the fuel battery cell. The fuel battery cell according to the present invention is provided with a first and a second insulating films between a support substrate and a first electrode. The support substrate has a first opening, the first insulating film has a second opening, and the second insulating film has a third opening. An opening area of the first opening is larger than that of the second opening, and an opening area of the third opening is larger than that of the second opening (see FIG. 2).

Abstract: An object of the invention is to increase the output power of a solid oxide fuel cell by making a lower electrode layer porous so as to form a three-phase interface and reducing a thickness of a solid electrolyte layer to 1 micrometer or less. A fuel cell according to the invention includes a first electrode layer at a position where an opening formed in a board is covered, and a solid electrolyte layer having a thickness of 1000 nm or less. At least a part of a region of the first electrode layer covering the opening is porous (see FIG. 5).

Abstract: The present invention aims to reduce a failure in a fuel cell module and reduce manufacturing costs by specifying and taking countermeasures against cells in short-circuit failure from among fuel cells manufactured on a substrate by using a thin-film deposition process. In a fuel cell array according to the present invention, each fuel cell includes a solid electrolyte layer between a first electrode layer and a second electrode layer. A first wiring is connected to the second electrode layer, and a second wiring is connected to the first electrode layer through a connection element. The connection element is formed by sandwiching a conductive layer between two electrodes (refer to FIG. 8).

Abstract: A control device according to an embodiment includes a storage, a determining unit, and a driving unit. The storage stores therein information on a hysteresis area of an actuator. The determining unit determines, based on a control mode, a target current value according to the hysteresis area whose information is stored in the storage. The driving unit supplies a driving current according to the target current value determined by the determining unit to the actuator.

Abstract: A control device according to an embodiment includes a storage, a determining unit, and a driving unit. The storage stores therein information on a hysteresis area of an actuator. The determining unit determines, based on a control mode, a target current value according to the hysteresis area whose information is stored in the storage. The driving unit supplies a driving current according to the target current value determined by the determining unit to the actuator.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×107 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: A Schottky junction type semiconductor device in which the opening width of a trench can be decreased without deteriorating the withstanding voltage. The cross sectional shape of a trench has a shape of a sub-trench in which the central portion is higher and the periphery is lower at the bottom of the trench, and a p type impurity is introduced vertically to the surface of the drift layer thereby forming a p+ SiC region, which is formed in contact to the inner wall of the trench having the sub-trench disposed therein, such that the junction position is formed more deeply in the periphery of the bottom of the trench than the junction position in the central portion of the bottom of the trench.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.