Patents by Inventor Natsuki Yokoyama
Natsuki Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9048264Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.Type: GrantFiled: March 20, 2014Date of Patent: June 2, 2015Assignee: Renesas Electronics CorporationInventors: Yasuaki Kagotoshi, Koichi Arai, Natsuki Yokoyama, Haruka Shimizu
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Patent number: 9041049Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: GrantFiled: August 19, 2013Date of Patent: May 26, 2015Assignee: Renesas Electronics CorporationInventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Publication number: 20150060887Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: ApplicationFiled: November 9, 2014Publication date: March 5, 2015Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Publication number: 20150041829Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: ApplicationFiled: September 24, 2014Publication date: February 12, 2015Inventors: Haruka SHIMIZU, Natsuki YOKOYAMA
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Patent number: 8890278Abstract: Reliability of a semiconductor device is improved by suppressing reverse voltage deterioration at the time of reverse bias junction barrier Schottky diode using a substrate containing SiC. In a JBS diode having an active area of 0.1 cm2 or more, an area of a Schottky interface at which a drift layer and a Schottky electrode are contacted can be sufficiently reduced by relatively increasing a ratio of p-type semiconductor region being a junction barrier region in an active region, and thereby deterioration in reverse voltage caused by defects existing in the drift layer is prevented.Type: GrantFiled: October 25, 2012Date of Patent: November 18, 2014Assignee: Hitachi, Ltd.Inventors: Norifumi Kameshiro, Natsuki Yokoyama
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Patent number: 8872191Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: GrantFiled: October 18, 2012Date of Patent: October 28, 2014Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20140284625Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.Type: ApplicationFiled: March 20, 2014Publication date: September 25, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yasuaki KAGOTOSHI, Koichi ARAI, Natsuki YOKOYAMA, Haruka SHIMIZU
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Patent number: 8766277Abstract: The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.Type: GrantFiled: February 3, 2011Date of Patent: July 1, 2014Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20130334542Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: ApplicationFiled: August 19, 2013Publication date: December 19, 2013Applicant: Renesas Electronics CorporationInventors: Koichi ARAI, Yasuaki KAGOTOSHI, Nobuo MACHIDA, Natsuki YOKOYAMA, Haruka SHIMIZU
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Patent number: 8564060Abstract: There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.Type: GrantFiled: July 12, 2010Date of Patent: October 22, 2013Assignee: Hitachi, Ltd.Inventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20130244407Abstract: A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step.Type: ApplicationFiled: April 30, 2013Publication date: September 19, 2013Inventors: Natsuki YOKOYAMA, Tomoyuki SOMEYA
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Patent number: 8524552Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: GrantFiled: January 31, 2012Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Publication number: 20130140584Abstract: Disclosed is a JBS diode wherein an increase in an on-voltage is suppressed by sufficiently spreading a current to the lower portion of a junction barrier (p+) region. The JBS diode has a structure, which has an n region having a relatively high concentration compared with the n? drift layer concentration, said n region being in the lower portion of the junction barrier (p+) region.Type: ApplicationFiled: June 2, 2010Publication date: June 6, 2013Inventors: Norifumi Kameshiro, Natsuki Yokoyama
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Patent number: 8445352Abstract: A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step.Type: GrantFiled: November 11, 2008Date of Patent: May 21, 2013Assignee: Hitachi, Ltd.Inventors: Natsuki Yokoyama, Tomoyuki Someya
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Patent number: 8436397Abstract: In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.Type: GrantFiled: December 16, 2009Date of Patent: May 7, 2013Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20130056754Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: ApplicationFiled: October 18, 2012Publication date: March 7, 2013Inventors: Haruka SHIMIZU, Natsuki YOKOYAMA
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Patent number: 8390001Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: GrantFiled: March 8, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20120193641Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Patent number: 8203150Abstract: A buffer layer configured of the same conductive semiconductor layers of two or more layers as a drift layer is installed by epitaxial growth between a first semiconductor layer configuring the drift layer that is a layer in which components of the semiconductor device are made and a base substrate including a silicon carbide single crystal wafer. A step of donor concentration is provided at an interface between the drift layer and the buffer layer, an interface between the semiconductor layers configuring the buffer layer, and an interface between the buffer layer and the base substrate and the donor concentration of the drift layer side is lower than that of the base substrate side, thereby making it possible to convert most basal plane dislocations into threading edge dislocations as compared to the drift layer having one layer or the buffer layer configured of one layer.Type: GrantFiled: May 28, 2009Date of Patent: June 19, 2012Assignee: Hitachi Cable, Ltd.Inventors: Toshiyuki Ohno, Natsuki Yokoyama, Hajime Goto
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Patent number: 8129802Abstract: In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.Type: GrantFiled: July 2, 2008Date of Patent: March 6, 2012Assignee: Hitachi, Ltd.Inventors: Hiroshi Fukuda, Tsukasa Fujimori, Natsuki Yokoyama, Yuko Hanaoka, Takafumi Matsumura