Patents by Inventor Natsuki Yokoyama
Natsuki Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7325457Abstract: A sensor and sensor module with small power consumption and high reliability are disclosed. The sensor includes a capacitor having a capacitance varying with a physical quantity, a capacitance-voltage conversion circuit for converting the capacitance of the capacitor into a voltage, and a control signal generation circuit for generating a plurality of control signals. The capacitor has a frequency-capacitance characteristic with a resonant frequency. In a measurement of the physical quantity, the capacitance of the capacitor is measured with one of the control signals having a first frequency which is much higher or much lower than the resonant frequency. In a self-diagnosis of the sensor, the capacitance of the capacitor is measured with another one of the control signals having a second frequency which is equal or close to the resonant frequency.Type: GrantFiled: July 26, 2006Date of Patent: February 5, 2008Assignee: Hitachi, Ltd.Inventors: Tsukasa Fujimori, Natsuki Yokoyama, Hiroshi Fukuda, Yuko Hanaoka, Takashi Azuma
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Patent number: 7310563Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.Type: GrantFiled: December 30, 2005Date of Patent: December 18, 2007Assignee: Renesas Technology Corp.Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
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Patent number: 7306990Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).Type: GrantFiled: November 28, 2003Date of Patent: December 11, 2007Assignee: Japan Science & Technology AgencyInventors: Shinya Yamaguchi, Masahiko Ando, Toshikazu Shimada, Natsuki Yokoyama, Shunri Oda, Nobuyoshi Koshida
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Publication number: 20070262401Abstract: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.Type: ApplicationFiled: July 23, 2007Publication date: November 15, 2007Inventors: Natsuki Yokoyama, Shuntaro Machida, Yasushi Goto
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Publication number: 20070241427Abstract: In conventional mesa-type npn bipolar transistors, the improvement of a current gain and the miniaturization of the transistor have been unachievable simultaneously as a result of a trade-off being present between lateral diffusion and recombination of the electrons which have been injected from an emitter layer into a base layer, and a high-density base contact region—emitter mesa distance. In contrast to the above, the present invention is provided as follows: The gradient of acceptor density in the depth direction of a base layer is greater at the edge of an emitter layer than at the edge of a collector layer. Also, the distance between a first mesa structure including the emitter layer and the base layer, and a second mesa structure including the base layer and the collector layer, is controlled to range from 3 ?m to 9 ?m.Type: ApplicationFiled: March 15, 2007Publication date: October 18, 2007Inventors: Kazuhiro Mochizuki, Natsuki Yokoyama
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Patent number: 7270012Abstract: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.Type: GrantFiled: September 29, 2005Date of Patent: September 18, 2007Assignee: Hitachi, Ltd.Inventors: Natsuki Yokoyama, Shuntaro Machida, Yasushi Goto
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Publication number: 20070102831Abstract: The present invention has a object to enhance the yield and facilitate bonding in a device provided with micro-mechanical elements formed by a MEMS technique. According to the inveniton, when a first wafer having a plurality of areas in which micro-mechanical elements and pads are formed and a second wafer in which an aperture is formed are to be glued together, the aperture is shared by the pads in the plurality of areas. This makes it possible for individual chips, into which the wafer is cut out, to be bonded with a conventionally used wire bonder because a sufficient aperture is provided above the pads. Further according to the invention, at the step of dicing two glued wafers into individual chips, the two wafers are separately cut. This enables chipping of the wafers to be reduced and the yield at the dicing step to be enhanced.Type: ApplicationFiled: December 24, 2003Publication date: May 10, 2007Inventors: Shuntaro Machida, Natsuki Yokoyama, Yasushi Goto
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Patent number: 7199022Abstract: In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.Type: GrantFiled: April 1, 2004Date of Patent: April 3, 2007Assignee: Renesas Technology Corp.Inventors: Kan Yasui, Toshiyuki Mine, Yasushi Goto, Natsuki Yokoyama
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Publication number: 20070068266Abstract: A sensor and sensor module with small power consumption and high reliability are disclosed. The sensor includes a capacitor having a capacitance varying with a physical quantity, a capacitance-voltage conversion circuit for converting the capacitance of the capacitor into a voltage, and a control signal generation circuit for generating a plurality of control signals. The capacitor has a frequency-capacitance characteristic with a resonant frequency. In a measurement of the physical quantity, the capacitance of the capacitor is measured with one of the control signals having a first frequency which is much higher or much lower than the resonant frequency. In a self-diagnosis of the sensor, the capacitance of the capacitor is measured with another one of the control signals having a second frequency which is equal or close to the resonant frequency.Type: ApplicationFiled: July 26, 2006Publication date: March 29, 2007Inventors: Tsukasa Fujimori, Natsuki Yokoyama, Hiroshi Fukuda, Yuko Hanaoka, Takashi Azuma
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Patent number: 7196384Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogenType: GrantFiled: November 14, 2005Date of Patent: March 27, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Shimpei Tsujikawa, Toshiyuki Mine, Jiro Yugami, Natsuki Yokoyama, Tsuyoshi Yamauchi
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Patent number: 7193281Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.Type: GrantFiled: December 8, 2005Date of Patent: March 20, 2007Assignee: Renesas Technology Corp.Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
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Patent number: 7115943Abstract: A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.Type: GrantFiled: December 17, 2004Date of Patent: October 3, 2006Assignee: Renesas Technology Corp.Inventors: Toshiyuki Mine, Natsuki Yokoyama, Kan Yasui
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Publication number: 20060205106Abstract: In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.Type: ApplicationFiled: August 23, 2005Publication date: September 14, 2006Inventors: Hiroshi Fukuda, Tsukasa Fujimori, Natsuki Yokoyama, Yuko Hanaoka, Takafumi Matsumura
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Patent number: 7064400Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.Type: GrantFiled: December 2, 2004Date of Patent: June 20, 2006Assignee: Renesas Technology Corp.Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
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Patent number: 7062344Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.Type: GrantFiled: November 17, 2003Date of Patent: June 13, 2006Assignee: Renesas Technology Corp.Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
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Publication number: 20060111805Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.Type: ApplicationFiled: December 30, 2005Publication date: May 25, 2006Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
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Publication number: 20060111802Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.Type: ApplicationFiled: December 30, 2005Publication date: May 25, 2006Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
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Patent number: 7045843Abstract: Disclosed herein is a latchable MEMS switch device capable of retaining its ON or OFF state even after the external power source is turned off. It is unnecessary not only to introduce novel materials such as magnetic material but also to form complicated structures. At least one of the cantilever and pull-down electrode of a cold switch is connected to a second MEMS switch. A capacitor between the cantilever and pull-down electrode of the cold switch is charged by the second MEMS switch. Thereafter since the cold switch is isolated in the device, the charge remains stored. Therefore, the cold switch can remain in the ON state since the charge continues to create electrostatic attraction between the cantilever and the pull-down electrode.Type: GrantFiled: March 1, 2004Date of Patent: May 16, 2006Assignee: Hitachi, Ltd.Inventors: Yasushi Goto, Shuntaro Machida, Natsuki Yokoyama
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Publication number: 20060081949Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.Type: ApplicationFiled: December 8, 2005Publication date: April 20, 2006Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
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Publication number: 20060070449Abstract: The method for promoting the size reduction, the performance improvement and the reliability improvement of a semiconductor device embedded with pressure sensor is provided. In a semiconductor device embedded with pressure sensor, a part of an uppermost wiring is used as a lower electrode of a pressure detecting unit. A part of a silicon oxide film formed on the lower electrode is a cavity. On a tungsten silicide film formed on the silicon oxide film, a silicon nitride film is formed. The silicon nitride film has a function to fill a hole or holes and suppress immersion of moisture from outside to the semiconductor device embedded with pressure sensor. A laminated film of the silicon nitride film and the tungsten silicide film forms a diaphragm of the pressure sensor.Type: ApplicationFiled: September 29, 2005Publication date: April 6, 2006Inventors: Natsuki Yokoyama, Shuntaro Machida, Yasushi Goto