Patents by Inventor Natsuki Yokoyama

Natsuki Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060068561
    Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen
    Type: Application
    Filed: November 14, 2005
    Publication date: March 30, 2006
    Inventors: Shimpei Tsujikawa, Toshiyuki Mine, Jiro Yugami, Natsuki Yokoyama, Tsuyoshi Yamauchi
  • Publication number: 20060051920
    Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).
    Type: Application
    Filed: November 28, 2003
    Publication date: March 9, 2006
    Inventors: Shinya Yamaguchi, Masahiko Ando, Toshikazu Shimada, Natsuki Yokoyama, Shunri Oda, Nobuyoshi Koshida
  • Patent number: 6982468
    Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: January 3, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shimpei Tsujikawa, Toshiyuki Mine, Jiro Yugami, Natsuki Yokoyama, Tsuyoshi Yamauchi
  • Publication number: 20050272198
    Abstract: Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed. For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.
    Type: Application
    Filed: June 6, 2005
    Publication date: December 8, 2005
    Inventors: Hirotaka Hamamura, Toshiyuki Mine, Natsuki Yokoyama
  • Publication number: 20050199940
    Abstract: A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.
    Type: Application
    Filed: December 17, 2004
    Publication date: September 15, 2005
    Inventors: Toshiyuki Mine, Natsuki Yokoyama, Kan Yasui
  • Patent number: 6897104
    Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: May 24, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shimpei Tsujikawa, Toshiyuki Mine, Jiro Yugami, Natsuki Yokoyama, Tsuyoshi Yamauchi
  • Publication number: 20050104141
    Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.
    Type: Application
    Filed: December 2, 2004
    Publication date: May 19, 2005
    Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
  • Publication number: 20050104621
    Abstract: The present invention relates to an LSI in which functions can be changed, and realizes, particularly, a system LSI in which functions are changed by changing connections of the circuit by use of MEMS switches. A bistable MEMS switch which can maintain states, and exhibits optimal stitching property, i.e., the switch has a very small resistance of several ? or less in an on-state, and has an infinite resistance in an off-state; is employed. An element in which functions can be changed during operation, is produced by utilizing a wiring layer of a CMOS semiconductor to form the MEMS switch. A semiconductor device exhibiting high-degree of freedom for changing functions, high-speed, and having small area, is realized.
    Type: Application
    Filed: September 3, 2004
    Publication date: May 19, 2005
    Inventors: Takayuki Kawahara, Masayuki Miyazaki, Yasushi Goto, Natsuki Yokoyama, Takahiro Onai
  • Publication number: 20050067621
    Abstract: Disclosed herein is a latchable MEMS switch device capable of retaining its ON or OFF state even after the external power source is turned off. It is unnecessary not only to introduce novel materials such as magnetic material but also to form complicated structures. At least one of the cantilever and pull-down electrode of a cold switch is connected to a second MEMS switch. A capacitor between the cantilever and pull-down electrode of the cold switch is charged by the second MEMS switch. Thereafter since the cold switch is isolated in the device, the charge remains stored. Therefore, the cold switch can remain in the ON state since the charge continues to create electrostatic attraction between the cantilever and the pull-down electrode.
    Type: Application
    Filed: March 1, 2004
    Publication date: March 31, 2005
    Inventors: Yasushi Goto, Shuntaro Machida, Natsuki Yokoyama
  • Publication number: 20050029600
    Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen
    Type: Application
    Filed: September 16, 2004
    Publication date: February 10, 2005
    Inventors: Shimpei Tsujikawa, Toshiyuki Mine, Jiro Yugami, Natsuki Yokoyama, Tsuyoshi Yamauchi
  • Patent number: 6833296
    Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: December 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
  • Publication number: 20040198019
    Abstract: In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 7, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Kan Yasui, Toshiyuki Mine, Yasushi Goto, Natsuki Yokoyama
  • Publication number: 20040159889
    Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 19, 2004
    Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
  • Publication number: 20040107020
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Application
    Filed: November 17, 2003
    Publication date: June 3, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 6710383
    Abstract: There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: March 23, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Jiro Yugami, Natsuki Yokoyama, Toshiyuki Mine, Yasushi Goto
  • Patent number: 6677230
    Abstract: A layer comprising a second metal silicide as a major constituent element or a layer comprising a second metal as a major constituent element is formed simultaneously by one single chemical vapor deposition process to the bottom surface of two out of there groups of openings etched in a dielectric film on a substrate. A surface comprising silicon as a major constituent element is exposed at each bottom (“through holes or local interconnection holes”) of the first group of openings, a surface comprising a first metal silicide as a major constituent element is exposed at each bottom of the second group of openings, and a surface comprising a first metal as a major constituent element is exposed at each bottom of the third group of openings. The manufacturing method provides low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections, even if the etched area of the openings are of different depths, shapes, or sizes.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: January 13, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Natsuki Yokoyama, Masakazu Kawano
  • Publication number: 20030228725
    Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen
    Type: Application
    Filed: June 3, 2003
    Publication date: December 11, 2003
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shimpei Tsujikawa, Toshiyuki Mine, Jiro Yugami, Natsuki Yokoyama, Tsuyoshi Yamauchi
  • Patent number: 6498100
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: December 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Publication number: 20020182847
    Abstract: A layer comprising a second metal silicide as a major constituent element or a layer comprising a second metal as a major constituent element is formed simultaneously by one single chemical vapor deposition process to the bottom surface of two out of there groups of openings etched in a dielectric film on a substrate. A surface comprising silicon as a major constituent element is exposed at each bottom (“through holes or local interconnection holes”) of the first group of openings, a surface comprising a first metal silicide as a major constituent element is exposed at each bottom of the second group of openings, and a surface comprising a first metal as a major constituent element is exposed at each bottom of the third group of openings. The manufacturing method provides low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections, even if the etched area of the openings are of different depths, shapes, or sizes.
    Type: Application
    Filed: July 18, 2002
    Publication date: December 5, 2002
    Applicant: Hitachi, Ltd. And Hitachi ULSI Systems Co., Ltd.
    Inventors: Natsuki Yokoyama, Masakazu Kawano
  • Patent number: 6461957
    Abstract: A layer comprising a second metal silicide as a major constituent element or a layer comprising a second metal as a major constituent element is formed simultaneously by one single chemical vapor deposition process to the bottom surface of two out of there groups of openings etched in a dielectric film on a substrate. A surface comprising silicon as a major constituent element is exposed at each bottom (“through holes or local interconnection holes”) of the first group of openings, a surface comprising a first metal silicide as a major constituent element is exposed at each bottom of the second group of openings, and a surface comprising a first metal as a major constituent element is exposed at each bottom of the third group of openings. The manufacturing method provides low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections, even if the etched area of the openings are of different depths, shapes, or sizes.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: October 8, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Natsuki Yokoyama, Masakazu Kawano