Patents by Inventor Nelson Felix
Nelson Felix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11226561Abstract: A self-priming resist may be formed from a first random copolymer forming a resist and a polymer brush having the general formula poly(A-r-B)-C-D, wherein A is a first polymer unit, B is a second polymer unit, wherein A and B are the same or different polymer units, C is a cleavable unit, D is a grafting group and r indicates that poly(A-r-B) is a second random copolymer formed from the first and second polymer units. The first random copolymer may be the same or different from the second random polymer. The self-priming resist can create a one-step method for forming an adhesion layer and resist by using the resist/brush blend.Type: GrantFiled: August 11, 2018Date of Patent: January 18, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chi-Chun Liu, Indira Seshadri, Kristin Schmidt, Nelson Felix, Daniel Sanders, Jing Guo, Ekmini Anuja De Silva, Hoa Truong
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Publication number: 20220013405Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Inventors: Nelson Felix, Ekmini Anuja De Silva, Luciana Meli Thompson, Yann Mignot
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Publication number: 20210398816Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.Type: ApplicationFiled: September 6, 2021Publication date: December 23, 2021Inventors: Nelson Felix, Ekmini Anuja De Silva, Praveen Joseph, Ashim Dutta
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Patent number: 11199778Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.Type: GrantFiled: March 12, 2019Date of Patent: December 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jing Guo, Bharat Kumar, Ekmini A. De Silva, Jennifer Church, Dario Goldfarb, Nelson Felix
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Patent number: 11192101Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.Type: GrantFiled: May 22, 2019Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Chi-Chun Liu, Yann Mignot, Joshua T. Smith, Bassem M. Hamieh, Nelson Felix, Robert L. Bruce
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Patent number: 11195995Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.Type: GrantFiled: January 6, 2020Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Chi-Chun Liu, Yann Mignot, Ekmini Anuja De Silva, Nelson Felix, John Christopher Arnold
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Patent number: 11177130Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.Type: GrantFiled: May 6, 2019Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Ekmini Anuja De Silva, Dario Goldfarb, Nelson Felix, Daniel Corliss, Rudy J. Wojtecki
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Patent number: 11164772Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.Type: GrantFiled: October 30, 2018Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nelson Felix, Ekmini Anuja De Silva, Luciana Meli Thompson, Yann Mignot
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Publication number: 20210325784Abstract: An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.Type: ApplicationFiled: April 16, 2020Publication date: October 21, 2021Inventors: Abraham Arceo de la Pena, Jennifer Church, Nelson Felix, Ekmini Anuja De Silva
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Patent number: 11131919Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.Type: GrantFiled: June 22, 2018Date of Patent: September 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yongan Xu, Zhenxing Bi, Yann Mignot, Nelson Felix, Ekmini A. De Silva
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Patent number: 11133260Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.Type: GrantFiled: November 15, 2019Date of Patent: September 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chi-Chun Liu, John C. Arnold, Dominik Metzler, Nelson Felix, Ashim Dutta
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Patent number: 11133195Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.Type: GrantFiled: April 30, 2019Date of Patent: September 28, 2021Assignee: International Business Machines CorporationInventors: Nelson Felix, Ekmini Anuja De Silva, Praveen Joseph, Ashim Dutta
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Publication number: 20210288164Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Inventors: Tao Li, Indira SESHADRI, NELSON FELIX, ERIC MILLER
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Patent number: 11121024Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.Type: GrantFiled: August 16, 2019Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekmini A. De Silva, Nelson Felix, Indira Seshadri, Stuart A. Sieg
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Patent number: 11084032Abstract: A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.Type: GrantFiled: May 22, 2019Date of Patent: August 10, 2021Assignee: International Business Machines CorporationInventors: Chi-Chun Liu, Yann Mignot, Joshua T. Smith, Bassem M. Hamieh, Nelson Felix, Robert L. Bruce
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Patent number: 11067896Abstract: A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.Type: GrantFiled: December 17, 2019Date of Patent: July 20, 2021Assignee: International Business Machines CorporationInventors: Cody John Murray, Ekmini Anuja De Silva, Alex Richard Hubbard, Karen Elizabeth Petrillo, Nelson Felix
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Publication number: 20210210679Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.Type: ApplicationFiled: January 6, 2020Publication date: July 8, 2021Inventors: Chi-Chun Liu, Yann Mignot, Ekmini Anuja De Silva, Nelson Felix, John Christopher Arnold
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Patent number: 11054250Abstract: An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.Type: GrantFiled: April 11, 2018Date of Patent: July 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gangadhara Raja Muthinti, Chiew-Seng Koay, Siva Kanakasabapathy, Nelson Felix
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Patent number: 11037786Abstract: A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.Type: GrantFiled: May 6, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Ekmini Anuja De Silva, Dario Goldfarb, Nelson Felix, Daniel Corliss, Rudy J. Wojtecki
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Publication number: 20210151377Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.Type: ApplicationFiled: November 15, 2019Publication date: May 20, 2021Inventors: Chi-Chun Liu, John C. Arnold, Dominik Metzler, Nelson Felix, Ashim Dutta