Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

Abstract: A photolithography patterning stack and method for repairing defects in the stack. The stack includes an organic planarization layer, a hardmask layer, and a plurality of patterned photoresist lines in contact with the hardmask layer. A plurality of trenches is situated between the plurality of patterned photoresist lines. Each trench exposes a portion of the hardmask layer. A repairing layer is formed in contact with and only bonded to surfaces of the plurality of patterned photoresist lines. The method includes forming a photolithographic patterning stack. The stack includes at least a hardmask layer formed on one or more underlayers and a photoresist layer formed in contact with the hardmask layer. The photoresist layer is patterned into a plurality of patterned portions. A repairing layer is formed in contact with and only bonded to surfaces of each patterned portion of the plurality of portions.

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: Embodiments of the present invention are directed to the wet stripping of an organic planarization layer (OPL) using reversible UV crosslinking and de-crosslinking. In a non-limiting embodiment of the invention, an interlayer dielectric is formed over a substrate. A trench is formed in the interlayer dielectric. A work function metal is formed over the interlayer dielectric such that a portion of the work function metal partially fills the trench. A UV sensitive OPL is formed over the work function metal such that a portion of the UV sensitive OPL fills the trench. The UV sensitive OPL can be crosslinked by applying light at a first UV frequency and de-crosslinked by applying light at a second UV frequency.

Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

Abstract: A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.

Abstract: A wafer element with a tight-pitch formation is provided. The wafer element includes an alternating material hard mask comprising a repeating array of abutting first, second and third vertical elements. The first, second and third vertical elements are formed of first, second and third materials, respectively. The first material is selectively etchable with respect to the second and third materials, the second material is selectively etchable with respect to the first and third materials and the third material is selectively etchable with respect to the first and second materials.

Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Abstract: A self-priming resist may be formed from a first random copolymer forming a resist and a polymer brush having the general formula poly(A-r-B)-C-D, wherein A is a first polymer unit, B is a second polymer unit, wherein A and B are the same or different polymer units, C is a cleavable unit, D is a grafting group and r indicates that poly(A-r-B) is a second random copolymer formed from the first and second polymer units. The first random copolymer may be the same or different from the second random polymer. The self-priming resist can create a one-step method for forming an adhesion layer and resist by using the resist/brush blend.

Abstract: A semiconductor structure comprises a semiconductor substrate, and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack comprises at least a hard mask layer and a resist layer formed over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on a developed pattern of the resist layer through inclusion in the hard mask layer of one or more materials inhibiting deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer. The hard mask layer illustratively comprises, for example, at least one of a grafted self-assembled monolayer configured to inhibit deposition of the metal-containing layer, and a grafted polymer brush material configured to inhibit deposition of the metal-containing layer.

Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.

Abstract: A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.

Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

Abstract: A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Abstract: An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.