Abstract: A method for fabricating a semiconductor device includes forming a plurality of mandrel cuts from a first set of mandrels of a base structure using lithography, surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures, forming a flowable material layer on exposed surfaces of the mandrel-spacer structures, and performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

Abstract: A method of forming a semiconductor structure includes forming one or more interconnect lines, the one or more interconnect lines including trenches of a first metal material surrounded by a first interlayer dielectric layer. The method also includes forming pillars of a second metal material different than the first metal material over the one or more interconnect lines utilizing a metal on metal growth process, and forming an etch stop dielectric layer, the pillars of the second metal material shaping the etch stop dielectric layer. The method further includes forming one or more vias to the one or more interconnect lines, the one or more vias being fully aligned to the one or more interconnect lines using the etch stop dielectric layer.

Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: Techniques for semiconductor process flow disposition optimization using clamped Monte Carlo distribution are provided. In one aspect, a method for optimizing a semiconductor fabrication process includes: providing a model of the fabrication process; identifying sensitive parameters of the fabrication process using Monte Carlo simulations that sample sections of experimental parameter populations from the fabrication process as input to the model to determine parameters which impact an outcome of the Monte Carlo simulations, wherein the parameters which impact the outcome of the Monte Carlo simulations are the sensitive parameters; bounding the experimental parameter populations of the sensitive parameters to improve the outcome of the Monte Carlo simulations; and modifying the fabrication process based on the providing, identifying and bounding steps to improve an output of the fabrication process.

Abstract: A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.

Abstract: Photoactive polymer brush materials and methods for EUV photoresist patterning using the photoactive polymer brush materials are described. The photoactive polymer brush material incorporates a grafting moiety that can be immobilized at the substrate surface, a dry developable or ashable moiety, and a photoacid generator moiety, which are bound to a polymeric backbone. The photoacid generator moiety generates an acid upon exposure to EUV radiation acid at the interface, which overcomes the acid depletion problem to reduce photoresist scumming. The photoacid generator moiety can also facilitate cleavage of the photoactive polymer brush material from the substrate via an optional acid cleavable grafting functionality for the grafting moiety. The dry developable or ashable moiety facilitates complete removal of the photoactive brush material from the substrate in the event there is residue present subsequent to development of the chemically amplified EUV photoresist.

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.

Abstract: A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

Abstract: A plurality of mandrels and silicon dioxide spacer structures are formed, with the spacer structures interdigitated between the mandrels. An organic planarization layer is applied, as are a thin oxide layer and a layer of photoresist patterned in hole tone over the oxide layer, thereby defining a domain. At least one hole is etched in the thin oxide layer and the organic planarization layer to expose a portion of a hard mask layer surface between the spacer structures. A selective polymer brush is applied, which grafts only to the exposed hard mask surface, followed by solvent rinsing the domain to remove ungrafted polymer brush. At least one precursor is infused to an etch resistant material into the polymer brush by a sequential infiltration synthesis process. The organic planarization layer is ashed to convert the infused precursor into oxide form to further enhance etch selectivity to the hard mask layer.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Abstract: A plurality of mandrels and silicon dioxide spacer structures are formed, with the spacer structures interdigitated between the mandrels. An organic planarization layer is applied, as are a thin oxide layer and a layer of photoresist patterned in hole tone over the oxide layer, thereby defining a domain. At least one hole is etched in the thin oxide layer and the organic planarization layer to expose a portion of a hard mask layer surface between the spacer structures. A selective polymer brush is applied, which grafts only to the exposed hard mask surface, followed by solvent rinsing the domain to remove ungrafted polymer brush. At least one precursor is infused to an etch resistant material into the polymer brush by a sequential infiltration synthesis process. The organic planarization layer is ashed to convert the infused precursor into oxide form to further enhance etch selectivity to the hard mask layer.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.