Abstract: A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.

Abstract: Embodiments of the present invention are directed to the wet stripping of an organic planarization layer (OPL) using reversible UV crosslinking and de-crosslinking. In a non-limiting embodiment of the invention, an interlayer dielectric is formed over a substrate. A trench is formed in the interlayer dielectric. A work function metal is formed over the interlayer dielectric such that a portion of the work function metal partially fills the trench. A UV sensitive OPL is formed over the work function metal such that a portion of the UV sensitive OPL fills the trench. The UV sensitive OPL can be crosslinked by applying light at a first UV frequency and de-crosslinked by applying light at a second UV frequency.

Abstract: Photoactive polymer brush materials and methods for EUV photoresist patterning using the photoactive polymer brush materials are described. The photoactive polymer brush material incorporates a grafting moiety that can be immobilized at the substrate surface, a dry developable or ashable moiety, and a photoacid generator moiety, which are bound to a polymeric backbone. The photoacid generator moiety generates an acid upon exposure to EUV radiation acid at the interface, which overcomes the acid depletion problem to reduce photoresist scumming. The photoacid generator moiety can also facilitate cleavage of the photoactive polymer brush material from the substrate via an optional acid cleavable grafting functionality for the grafting moiety. The dry developable or ashable moiety facilitates complete removal of the photoactive brush material from the substrate in the event there is residue present subsequent to development of the chemically amplified EUV photoresist.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: Embodiments of the present invention are directed to the wet stripping of an organic planarization layer (OPL) using reversible UV crosslinking and de-crosslinking. In a non-limiting embodiment of the invention, an interlayer dielectric is formed over a substrate. A trench is formed in the interlayer dielectric. A work function metal is formed over the interlayer dielectric such that a portion of the work function metal partially fills the trench. A UV sensitive OPL is formed over the work function metal such that a portion of the UV sensitive OPL fills the trench. The UV sensitive OPL can be crosslinked by applying light at a first UV frequency and de-crosslinked by applying light at a second UV frequency.

Abstract: Embodiments of the present invention are directed to the wet stripping of an organic planarization layer (OPL) using reversible UV crosslinking and de-crosslinking. In a non-limiting embodiment of the invention, an interlayer dielectric is formed over a substrate. A trench is formed in the interlayer dielectric. A work function metal is formed over the interlayer dielectric such that a portion of the work function metal partially fills the trench. A UV sensitive OPL is formed over the work function metal such that a portion of the UV sensitive OPL fills the trench. The UV sensitive OPL can be crosslinked by applying light at a first UV frequency and de-crosslinked by applying light at a second UV frequency.

Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.

Abstract: An alignment feature disposed on a substrate, the alignment feature including a first lithographic pattern having a first aggregate geometric center point defined by a first sub-pattern comprising alignment marks having a first sub-pattern geometric center point arranged a distance (d0) in a first direction from the first aggregate geometric center point, and a second sub-pattern comprising alignment marks having a second sub-pattern geometric center point arranged the distance d0 in a reciprocal direction of the first direction from the first aggregate geometric center point.

Abstract: An alignment feature disposed on a substrate, the alignment feature including a first lithographic pattern having a first aggregate geometric center point defined by a first sub-pattern comprising alignment marks having a first sub-pattern geometric center point arranged a distance (d0) in a first direction from the first aggregate geometric center point, and a second sub-pattern comprising alignment marks having a second sub-pattern geometric center point arranged the distance d0 in a reciprocal direction of the first direction from the first aggregate geometric center point.