Abstract: A multi-ladder DAC includes first and second resistor ladders, with a switch-interconnect. The switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRswitch error, thereby improving DNL.

Abstract: A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output node; and at least one cross-coupled switching circuit portion, each cross-coupled switching circuit portion comprising a first transistor having a drain connected to the first output node and a second transistor having a drain connected to the second output node, the first transistor having a gate connected between the drain of the second transistor and the second output node and the second transistor having a gate connected between the drain of the first transistor and the first output node, each of the first and second transistors having a threshold voltage that is determined to be the highest threshold voltage available for the process used to create the VCO.

Abstract: An oscillator architecture with pulse-edge tuning. The oscillator includes a signal generator generating at least two signal frequencies, and a logic circuit (such as an AND gate) that combines the signal frequencies to generate a corresponding oscillator signal. The logic circuit includes a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Duty cycle tuning/correction circuitry includes high and low side tuning FETs: a high-side tuning PMOS transistor is coupled between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor is coupled between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs (digital to analog converters) configure to provide a tuning control signals to the tuning FETs (variable resistance) based on respective input digital tuning/correction signals.

Abstract: A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Abstract: A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.

Abstract: A power-on-reset (POR) circuit is suitable for use in an integrated circuit including at least one CMOS logic block that includes PMOS and NMOS transistors respectively characterized by threshold voltages Vtp and Vtn, the CMOS circuitry operable with a power supply voltage Vdd. The POR circuit is operable to transition between a POR_active state and a POR_inactive state, including outputting a corresponding POR_state signal. The POR circuit includes: (a) VDD/VT threshold circuitry coupled to receive the Vdd voltage as an input to the POR circuit, and to provide a Vtp_threshold voltage based on Vdd and Vtp, and a Vtn_threshold voltage based on Vdd and Vtn; (b) POR transition detect circuitry coupled to the VDD/VT threshold circuitry to provide a POR_transition signal based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry coupled to the POR transition detect circuitry to provide the POW_state signal based on the POR_transition signal.

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Abstract: Noise-shaped frequency hopping power converters are disclosed. An example noise-shaped frequency hopping power converter comprises a shaped number generator having a first output to output a noise-shaped selection signal and a power converter having a first input to receive an input voltage signal, a second input to receive a switching signal that is based on the noise-shaped selection signal, and a second output to output an output voltage signal based on the switching signal.

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Abstract: A front-end receiver includes an amplifier that has a steady gain over a wide frequency range. The disclosed amplifier adopts an architecture in which a common-source (CS) circuit stacks against a common-gate (CG) circuit. The CG circuit provides the input impedance matching while the CS circuit boosts the amplification gain. As a result, the disclosed amplifier allows the front-end receiver to break free from a tradeoff between input impedance matching and gain boosting. Moreover, the disclosed amplifier achieves power saving and noise reduction by having the CS circuit to share the same bias current with the CG circuit.

Abstract: A signal profiler generates and monitors a signal profile corresponding to signal power (absolute or relative) per frequency band. The signal profiler includes a signal profile generator and a signal profile monitor. The signal profile generator processes a received signal in pre-defined frequency bands, and captures frequency-band signal power information into frequency bins, this frequency-binned signal power information constituting a signal profile. The signal profile monitor monitors the signal profile, including variations in the signal profile based on pre-defined criteria, and output corresponding profile-variation information (such as flags or interrupt requests). The signal profile generator is an FFT engine. The signal profile monitor is an FSM (finite state machine). An example application is use in a direct conversion wireless receiver to monitor relative image channel power as a signal profile variation that can be used to invoke QMC compensation/configuration.

Abstract: Triggered remote function calls can be used in master-slave systems to trigger slave-side software functions pre-loaded by a master into slave MCU memory, with associated parameters pre-loaded into a slave function interface memory. A master issues trigger-function signals (such as rising/falling edges or signal levels) over a trigger-function signal line. The slave includes a trigger conditioning block that in response issues a trigger-function request to the slave MCU, which calls/executes the associated software function, including accessing the associated trigger-function parameters from function interface memory. A slave can include a hardware function block with functionality configurable by a pre-loaded software configuration function (with associated parameters). A master can include a hardware function block configured to issue trigger-function signals.

Abstract: A front-end receiver includes an amplifier that has a steady gain over a wide frequency range. The disclosed amplifier adopts an architecture in which a common-source (CS) circuit stacks against a common-gate (CG) circuit. The CG circuit provides the input impedance matching while the CS circuit boosts the amplification gain. As a result, the disclosed amplifier allows the front-end receiver to break free from a tradeoff between input impedance matching and gain boosting. Moreover, the disclosed amplifier achieves power saving and noise reduction by having the CS circuit to share the same bias current with the CG circuit.

Abstract: A front-end receiver includes a first mixer of a first channel, a second mixer of a second channel, and a switching circuit that is configured to select the first mixer or the second mixer during a particular time period. Upon being selected, one of the first mixer or the second mixer is configured to deliver a down-converted signal that down-converts a respective RF signal of either the first or second reception channel. As the tasks of down-conversion and multiplexing are combined at the mixer level, the first and second reception channels may share a baseband circuit while being able to provide a well-balanced metrics of channel isolation, low noise figure, and linearity.

Abstract: A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.

Abstract: A system for reducing a local oscillator leakage component. The system includes a transmitter channel to transmit data modulated using a transmitter local oscillator frequency. A transmitted signal includes a transmitter local oscillator leakage component. The system also includes a receiver channel to receive the transmitted signal using a receiver local oscillator signal having a frequency offset from the transmitter local oscillator frequency. The received signal includes the transmitter local oscillator leakage component isolated from one or more receiver impairments. The system further includes a feedback loop from the receiver channel to the transmitter channel to identify a power of the isolated transmitter local oscillator leakage component and to generate a local oscillator leakage cancellation signal based on the identified power.

Abstract: A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output node; and at least one cross-coupled switching circuit portion, each cross-coupled switching circuit portion comprising a first transistor having a drain connected to the first output node and a second transistor having a drain connected to the second output node, the first transistor having a gate connected between the drain of the second transistor and the second output node and the second transistor having a gate connected between the drain of the first transistor and the first output node, each of the first and second transistors having a threshold voltage that is determined to be the highest threshold voltage available for the process used to create the VCO.

Abstract: A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd?) to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.

Abstract: A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector UP signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd?) to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.