Abstract: A wireless communication device includes at least two antennas with at least two corresponding receive chains. Selectively activating and deactivating the receivers as needed for a desired quality of reception controls the performance and power consumption of the wireless communication device. The wireless communication device may operate in a single receiver mode or a dual receiver diversity mode. In the dual receiver diversity mode, the wireless communication device may selectively control the gain of one or more antennas and/or reconfigure one or more receive chains to minimize power consumption while maintaining a desired performance.

Abstract: A quartz crystal oscillator comprises a balanced circuit with a quartz crystal resonator device connected in series resonance across a balanced, low-impedance node within a sustaining amplifier. A phase modulator such as a quadrature modulator is included in the feedback loop to allow programming of the loop phase shift thereby to alter the frequency point on the crystal resonance curve at which the circuit oscillates. The in-phase loop signal is hardlimited while the quadrature loop signal component is not hardlimited with the effect that the frequency control curve slope is more accurately defined. An active neutralization of the crystal's parasitic shunt capacitance is disclosed for obtaining a linear frequency control curve.

Abstract: A quartz crystal oscillator comprises a balanced circuit with a quartz crystal resonator device connected in series resonance across a balanced, low-impedance node within a sustaining amplifier. A phase modulator such as a quadrature modulator is included in the feedback loop to allow programming of the loop phase shift thereby to alter the frequency point on the crystal resonance curve at which the circuit oscillates. The in-phase loop signal is hardlimited while the quadrature loop signal component is not hardlimited with the effect that the frequency control curve slope is more accurately defined. An active neutralization of the crystal's parasitic shunt capacitance is disclosed for obtaining a linear frequency control curve.

Abstract: A programmable digital divider operates under the control of a division controller to derive a second synthesized frequency based on a first synthesized frequency. The programmable divider divides the first synthesized signal to derive the second synthesized signal. The division amount is an integer, but varies between integer values if necessary to achieve a non-integer average division value. The majority of the noise generated by the frequency synthesizer is generated away from the centerline frequency and is easily filtered by narrowband filter. The frequency synthesizer may optionally be incorporated into a modified phase-locked loop to generate the second synthesized signal. By using a digital divider, instead of a traditional phase-locked loop, these embodiments allow for integration of the frequency synthesizer onto an integrated circuit, thereby lowering cost and improving resistance to noise spurs. This approach is particularly suited to telecommunications applications.

Abstract: An Automatic Frequency Control (AFC) circuit for a mobile terminal employs a fractional-N Phase Locked Loop (PLL) to directly reduce errors in the synthesized frequency, such as due to component tolerances, temperature drift, and the like. The frequency error is detected by the average speed of rotation of the I,Q constellation. A corresponding offset is added to the tuning frequency selection word prior to encoding, such as in a &Dgr;&Sgr; modulator, to generate an effective non-integer PLL frequency division factor over a specified duration. The &Dgr;&Sgr; modulator may include dithering the different integer values by a pseudo-random number to minimize noise in the output frequency spectrum introduced by the fractional-N division. Component and parameter selection allow a high degree of resolution in frequency control of the fractional-N PLL. By directly controlling for the frequency error, a DAC and XTAL oscillator tuning circuit may be eliminated from the AFC circuit.

Abstract: A prescaler (200) includes a first frequency divider (204, 206) configured to receive an input signal at an input frequency. The prescaler further includes a phase rotator (208) coupled to the first frequency divider to produce a plurality of signal phases in response to the input signal. A frequency control circuit (214) is configured as a one-hot decoder to select one signal phase of the plurality of signal phases. The one-hot decoder provides maximum speed of operation of the prescaler by eliminating decoding of the feedback signal.

Abstract: A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2&pgr; radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Abstract: A phase-locked loop circuit having improved phase noise characteristics includes a voltage-controlled oscillator developing an oscillating output signal responsive to a voltage control input. A reference source provides a reference frequency signal. A phase detector is operatively connected to the voltage-controlled oscillator and the reference source developing an output proportional to a phase difference between the oscillating output signal and the reference frequency signal. A loop filter connects the phase detector output to the voltage control input. The loop filter includes a switched-capacitor equivalent resistor.

Abstract: A digital gain controlled VGA is provided having a built-in decoder allowing for more standardized design of radio receivers by allowing a standardized gain control signal to be sent to the digital gain controlled VGA for controlling gain of the digital gain controlled VGA. Additionally, a digital gain controlled VGA is provided which is able to be controlled using an analog gain control signal. Use of the analog gain control signal allows the problems associated with the fast update rate required by the digital gain control word to be overcome. In addition, a digital gain controlled VGA is provided having a programmable decoder and noise and linearity circuit for changing the noise and linearity characteristics of the digital gain controlled VGA during operation.

Abstract: An improved low noise oscillator operates by periodically opening a ring oscillator to insert a reference input, thereby resetting any accumulated timing errors. The ring oscillator may be placed within the PLL to function as a voltage controlled oscillator. The loop in the ring oscillator is opened immediately prior to the arrival of the reference signal edge. While the ring oscillator loop is open, the reference signal is fed to the initial inverter instead of the initial inverter of the ring oscillator receiving the output from the last inverter of the ring oscillator. Shortly thereafter, the ring oscillator loop is closed again, and the structure operates as a conventional PLL with a ring oscillator until the next reset. The switching of the ring oscillator input is accomplished via a switch operable between a ring setting (loop back ring oscillator output) and a reset setting (reference signal as input).

Abstract: A power conserving phase-locked loop achieves power savings by adding a switch which selectively enables the bias current for the charge pump associated with the phase comparator of the phase-locked loop. The switch is connected by a logic circuit to a counter that tracks the expected arrival time of a signal edge of the reference signal. Immediately prior to the arrival of the expected signal edge, the switch is enabled, thereby creating and applying the bias current to activate the charge pump in the event that a correction is needed to maintain the “lock” in the phase-locked loop. When the signal edge passes, the bias current is turned off again before the arrival of the next signal edge. This switching may result in a ten percent duty cycle in the biasing current, resulting in approximately a ninety percent power savings.

Abstract: An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge. The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting.

Abstract: A phase-locked loop circuit having improved phase noise characteristics includes a voltage-controlled oscillator developing an oscillating output signal responsive to a voltage control input. A reference source provides a reference frequency signal. A phase detector is operatively connected to the voltage-controlled oscillator and the reference source developing an output proportional to a phase difference between the oscillating output signal and the reference frequency signal. A loop filter connects the phase detector output to the voltage control input. The loop filter includes a switched-capacitor equivalent resistor.

Abstract: A current mirror circuit is disclosed including a reference device and a biased device, each having control, input and output elements, with the control element of the biased device operably connected to the control element of the reference device. A reference current source is connected to the input element of the reference device and produces a reference current flowing through the reference device, wherein a bias current is produced in the biased device as a multiple of the reference current. A compensation network is connected between the biased device and the reference device for maintaining a constant bias current in the biased device regardless of varying operating characteristics in at least one of the biased device and the reference device.

Abstract: A frequency doubling circuit includes a quadrature phase generator and a mixer coupled to the quadrature phase generator. The quadrature phase generator receives a reference signal having a reference frequency and generates first and second quadrature phase shifted signals having the reference frequency. The mixer receives the first and second quadrature phase shifted signals and generates an output signal having an output frequency twice that of the reference frequency. Related methods and communications devices are also discussed.

Abstract: A power-on reset circuit for resetting the register values contained on an integrated circuit upon power-up of the integrated circuit. The power-on reset circuit can be implemented either internal or external to the integrated circuit. The power-on reset circuit generates a reset signal as long as the supply voltage is not in the operational range and maintains the reset signal for a certain time after the supply voltage has returned to its nominal value. The power-on reset circuit also provides accurate detection of a serious supply voltage drop and has low power consumption. The power-on reset circuit comprises a battery, a voltage-referenced switching circuit, a current source, a capacitor and a voltage buffer.

Abstract: A transimpedance stage amplifier converts a current input signal at an input node to a low impedance output voltage at an output node. The amplifier includes a resistor connected between the input node and the output node. A feedback loop is connected across the resistor, the feedback loop comprising a transistor, the transistor using the current input signal as a biasing current.

Abstract: In a communication transceiver receiving a signal from a signal source defined by a source impedance between first and second nodes, an amplifier is provided having an input impedance matched to the source impedance. The amplifier includes a first transconductance cell having a first transconductance related to the input impedance and including first and second transistors each having control, supply and output elements. The first transconductance cell receives the signal from the signal source at the first and second control elements and develops a modified version of the signal as an output current signal at the first and second output elements, respectively. The first and second transistors are interconnected such that the control element of the first transistor is connected to the output element of the second transistor, and the control element of the second transistor is connected to the output element of the first transistor.

Abstract: A circuit for providing unity gain buffering of an input signal with reduced power consumption and symmetrical load driving capability. A feedback circuit between a buffer transistor and a bias circuit modulates the bias current to the buffer transistor. Modulating the bias current allows the buffer circuit to have a smaller quiescent bias current and increased current sink capability than the prior art unity gain buffer circuit. The modulating bias current allows more efficient operation of the buffer circuit while maintaining symmetrical load driving capability.

Abstract: In a communication transceiver receiving a signal from a signal source defined by a source impedance between first and second nodes, an amplifier is provided having an input impedance matched to the source impedance. The amplifier includes a transconductance cell having first and second transistors connected to the first and second nodes, respectively. The first and second transistors of the transconductance cell receive the signal from the signal source and develop a modified version of the signal as an output current signal at first and second output terminals, respectively. A first impedance circuit, having a first impedance related to the input impedance, is connected between the second node and the first transistor. Similarly, a second impedance circuit, having a second impedance related to the input impedance, is connected between the first node and the second transistor.