Patents by Inventor Norihito Tokura
Norihito Tokura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8102025Abstract: A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.Type: GrantFiled: February 22, 2007Date of Patent: January 24, 2012Assignee: DENSO CORPORATIONInventors: Yoshihiko Ozeki, Norihito Tokura, Yukio Tsuzuki
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Patent number: 8076718Abstract: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.Type: GrantFiled: September 28, 2005Date of Patent: December 13, 2011Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
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Publication number: 20110298446Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.Type: ApplicationFiled: June 1, 2011Publication date: December 8, 2011Applicant: DENSO CORPORATIONInventors: Satoshi SHIRAKI, Norihito Tokura, Shigeki Takahashi, Masahiro Yamamoto, Akira Yamada, Hiroyasu Kudo, Youichi Ashida, Akio Nakagawa
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Publication number: 20110291157Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.Type: ApplicationFiled: May 24, 2011Publication date: December 1, 2011Applicant: DENSO CORPORATIONInventors: Shigeki TAKAHASHI, Norihito Tokura, Satoshi Shiraki, Youichi Ashida, Akio Nakagawa
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Publication number: 20110073904Abstract: A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Applicant: DENSO CORPORATIONInventors: Youichi Ashida, Norihito Tokura, Shigeki Takahashi, Yoshiaki Nakayama, Satoshi Shiraki, Kouji Senda
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Patent number: 7692214Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ?1 and a thickness L1 of the first layer, a resistivity ?2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (?1/?2)×(L1·L2/W22)<1.6.Type: GrantFiled: March 20, 2007Date of Patent: April 6, 2010Assignee: DENSO CORPORATIONInventors: Norihito Tokura, Yukio Tsuzuki, Kenji Kouno
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Publication number: 20100060254Abstract: A synchronous-rectifier type DC-DC converter includes a high-side main switch element, a low-side rectifying switch element, and a control drive circuit. The rectifying switch element includes a rectifying transistor element and a rectifying diode element connected in antiparallel with the rectifying transistor element. The control drive circuit detects an input voltage to the main switch element and determines the input voltage or a rate of increase in the input voltage. When the determined value exceeds a predetermined reference value, a complementary ON/OFF operation of the main switch element and the rectifying transistor element is released, and a state where both the main switch element and the rectifying transistor element are kept OFF for a time period that is longer than a dead-time during the complementary ON/OFF operation is set.Type: ApplicationFiled: September 3, 2009Publication date: March 11, 2010Applicant: DENSO CORPORATIONInventors: Norihito Tokura, Hisato Kato, Norikazu Kanatake, Masakiyo Horie
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Patent number: 7667269Abstract: A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 ?m.Type: GrantFiled: April 6, 2006Date of Patent: February 23, 2010Assignee: DENSO CORPORATIONInventors: Yukio Tsuzuki, Norihito Tokura, Yoshihiko Ozeki, Kensaku Yamamoto
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Patent number: 7616859Abstract: A semiconductor device includes a spaced-channel IGBT and an antiparallel diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.Type: GrantFiled: June 12, 2008Date of Patent: November 10, 2009Assignee: DENSO CORPORATIONInventors: Norihito Tokura, Hiroki Sone, Shinji Amano, Hisato Kato
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Patent number: 7586151Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.Type: GrantFiled: May 11, 2005Date of Patent: September 8, 2009Assignees: Toyota Jidosha Kabushiki Kaisha, DENSO CORPORATIONInventors: Hidefumi Takaya, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
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Patent number: 7498634Abstract: A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.Type: GrantFiled: January 4, 2007Date of Patent: March 3, 2009Assignee: DENSO CORPORATIONInventors: Yukio Tsuzuki, Norihito Tokura
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Publication number: 20090001411Abstract: A semiconductor device includes a spaced-channel IGBT and an antiparalell diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.Type: ApplicationFiled: June 12, 2008Publication date: January 1, 2009Applicant: DENSO CORPORATIONInventors: Norihito Tokura, Hiroki Sone, Shinji Amano, Hisato Kato
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Patent number: 7470953Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.Type: GrantFiled: October 6, 2004Date of Patent: December 30, 2008Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura
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Publication number: 20080315248Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ?1 and a thickness L1 of the first layer, a resistivity ?2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (?1/?2)×(L1·L2/W22)<1.6.Type: ApplicationFiled: March 20, 2007Publication date: December 25, 2008Applicant: DENSO CORPORATIONInventors: Norihito Tokura, Yukio Tsuzuki, Kenji Kouno
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Patent number: 7456484Abstract: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.Type: GrantFiled: January 3, 2007Date of Patent: November 25, 2008Assignee: Denso CorporationInventors: Yoshihiko Ozeki, Norihito Tokura, Yukio Tsuzuki
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Publication number: 20070241394Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of terminal trench 62.Type: ApplicationFiled: May 11, 2005Publication date: October 18, 2007Inventors: Hidefumi Takaya, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
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Publication number: 20070200138Abstract: A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.Type: ApplicationFiled: February 22, 2007Publication date: August 30, 2007Applicant: DENSO CORPORATIONInventors: Yoshihiko Ozeki, Norihito Tokura, Yukio Tsuzuki
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Publication number: 20070170549Abstract: A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.Type: ApplicationFiled: January 4, 2007Publication date: July 26, 2007Applicant: DENSO CORPORATIONInventors: Yukio Tsuzuki, Norihito Tokura
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Publication number: 20070158680Abstract: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.Type: ApplicationFiled: January 3, 2007Publication date: July 12, 2007Applicant: DENSO CORPORATIONInventors: Yoshihiko Ozeki, Norihito Tokura, Yukio Tsuzuki
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Publication number: 20060289928Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.Type: ApplicationFiled: October 6, 2004Publication date: December 28, 2006Inventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura