Abstract: A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 ?m.

Abstract: A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

Abstract: In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.

Abstract: A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

Abstract: A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

Abstract: A vertical power MOSFET, which can improve a surge withstand voltage and a surge withstand voltage against a surge voltage from an inductance load L. The vertical power MOSFET has a plurality of unit cells. The unit cell is formed from a MOSFET that uses a p-type base layer at a sidewall of a rectangular U-groove as a channel portion. Each of the p-type base layer of each unit cell is connected each others Accordingly, it can restrain an impurity concentration of a corner portion (a portion positioned at a corner) of the rectangular p-type base layer from being decreased. Therefore, it can reduce the difference in distance from the end portion of the p-type base layer to the end portion of the depletion layer. As a result, it can improve the surge withstand voltage when a surge voltage is input from an inductance load L.

Abstract: In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.

Abstract: A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

Abstract: A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

Abstract: Insulated gate bipolar transistors which can restrain causing surge voltage due to an inductance component while an L-load is turned off and can improve a negative characteristic of a sustain voltage during breakdown. An insulated gate bipolar transistor (IGBT) is provided with: a p+-type semiconductor substrate; an n+-type buffer layer having high impurity concentration; an n-type intermediate layer; and an n−-type base layer having low impurity concentration. A p-type well layer and an n+-type emitter layer having high impurity concentration are formed in the n−-type base layer. The n-type intermediate layer has an intermediate impurity concentration between an impurity concentration of the n+-type buffer layer and that of the n−-type base layer. Thickness of the intermediate layer is determined so that the depletion layer does not reach the n+-type buffer layer even when the switching operation of the L-load is turned off.

Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

Abstract: A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12.

Abstract: A p-type silicon carbide semiconductor having a high carrier concentration and activation rate is provided by doping boron as an acceptor impurity in a single crystal silicon carbide. The boron occupies silicon sites in a crystal lattice of the single crystal silicon carbide.

Abstract: A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

Abstract: A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.

Abstract: A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

Abstract: An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

Abstract: A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench.

Abstract: A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.