Patents by Inventor Norihito Tokura

Norihito Tokura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5780953
    Abstract: In an on-vehicle alternator, both the magnetic flux variation frequency and maximum flux density are decreased sufficiently to thereby decrease the internal iron loss and thereby realize an increase in the current generation efficiency. The on-vehicle alternator comprises a rotor wherein magnetic pole cores that are polarized by a rotor coil to alternately different polarities are circumferentially disposed on the outer periphery thereof at prescribed equi-angular intervals. A permanent magnet which is embedded within a resin-made retainer body is provided between the magnetic pole cores and has side faces, as viewed circumferentially, which are polarized respectively to the same polarities as those of adjacent respective magnetic pole cores to thereby vary the magnetic flux quantity directed toward stator coils so as to exhibit a circumferential gentle curve.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: July 14, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Atsushi Umeda, Norihito Tokura, Hirohide Sato, Makoto Taniguchi, Shin Kusase
  • Patent number: 5776812
    Abstract: A manufacturing method of a MOSFET having a channel part on the side surface of a groove, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform. An n.sup.- -type epitaxial layer having a low impurity concentration is formed on a main surface of an n.sup.+ -type semiconductor substrate. This surface is specified as a main surface, and chemical dry etching is applied to a specified region of this main surface. A region including a surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film to a specified thickness. Following this process, p-type and n-type impurities are doubly diffused from the main surface to define the length of the channel and form a base layer and a source layer. Furthermore, the n.sup.+ -type semiconductor substrate is specified as a drain layer.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: July 7, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigeki Takahashi, Mitsuhiro Kataoka, Tsuyoshi Yamamoto, Yuuchi Takeuchi, Norihito Tokura
  • Patent number: 5753943
    Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: May 19, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Naoto Okabe, Makio Iida, Norihito Tokura
  • Patent number: 5744826
    Abstract: A semiconductor substrate 4 consisting of an n.sup.+ -type substrate 1, an n.sup.- -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3, made of hexagonal crystal-based single crystal silicon carbide with the main surface having a planar orientation approximately in the (0001) carbon face. An n.sup.+ -type source region 5 is formed in the surface layer of the semiconductor layer 3, and a trench 7 runs from the main surface through the region 5 and the semiconductor layer 3 reaching to the semiconductor layer 2, and extending approximately in the ?1120! direction.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: April 28, 1998
    Assignee: Denso Corporation
    Inventors: Yuichi Takeuchi, Takeshi Miyajima, Norihito Tokura, Hiroo Fuma, Toshio Murata
  • Patent number: 5723376
    Abstract: A groove is formed on the surface of a semiconductor substrate composed of silicon carbide and a first thermal oxidation film is formed by executing thermal oxidation on a damaged layer of groove inner walls. Then, the first thermal oxidation film is removed so that the damaged layer can be removed. Since a second thermal oxidation film is formed after the damaged layer is removed, the second thermal oxidation film is uniform. A silicon carbide semiconductor device can be achieved with less side etching because substantially a (0001) carbon face of a cubic system is chosen as the plane orientation of the semiconductor substrate.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: March 3, 1998
    Assignee: Nippondenso Co., LTD.
    Inventors: Yuuichi Takeuchi, Takeshi Miyajima, Kazukuni Hara, Norihito Tokura
  • Patent number: 5708352
    Abstract: An alternating current generator for motor vehicles having an extremely small power loss and which can be simply cooled includes a power converter having at least either high side semiconductor power elements or low side semiconductor elements. The high side power elements connect an output terminal of the armature coil to a high potential terminal of the battery; the low side semiconductor power elements connect an output terminal of the armature coil to a low potential terminal of the battery. The power converter converts the alternating current generated voltage of the armature coil into a direct current voltage to supply electricity to the battery. An exciting current controller includes a switching transistor for controlling an exciting current to a field coil. The semiconductor power elements in the power converter and/or the switching transistor in the exciting current controller are/is formed of SiC material, which is a compound of Si and C, having a resistivity smaller than that of pure Si.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: January 13, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Atsushi Umeda, Masatoshi Togawa, Junji Kawai, Hirohide Sato, Norihito Tokura
  • Patent number: 5698880
    Abstract: A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well.
    Type: Grant
    Filed: October 5, 1995
    Date of Patent: December 16, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigeki Takahashi, Mitsuhiro Kataoka, Tsuyoshi Yamamoto, Yuuichi Takeuchi, Norihito Tokura
  • Patent number: 5696396
    Abstract: A vertical MOSFET, which can control AC current flowing through a device only by the gate voltage, is obtained. On an n.sup.+ silicon layer is formed an n.sup.- silicon layer. Within the n.sup.- silicon layer is formed a p-body region. Within the p-body region is formed an n.sup.+ source region. On top of a substrate are formed a source electrode in contact only with the source region and a base electrode in contact only with the p-body region. The source electrode and the base electrode are connected to each other through a resistance at the outside. On a channel region is formed a gate electrode through a gate oxide film (insulating film). When the above semiconductor device is in the reverse bias conduction, the exciting current is controlled only by the gate voltage by setting the current flowing from a source terminal through the resistance to the base electrode, the p-body region and the n.sup.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: December 9, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Norihito Tokura, Kunihiko Hara, Takeshi Miyajima
  • Patent number: 5654560
    Abstract: A power semiconductor device having a current detecting function comprising a detection part that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 5, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Toshiaki Nishizawa, Akira Kuroyanagi, Tsuyoshi Yamamoto, Norihito Tokura
  • Patent number: 5608616
    Abstract: A power converter for an AC generator for motor vehicles for converting a generated voltage of the AC generator driven by an engine into a DC voltage to feed to a battery includes at least either high-side MOS power transistors for connecting an output end of an armature coil which generates the generated voltage of the AC generator with a high potential end of a battery or low-side MOS power transistors for connecting the output end of the armature coil with a low potential end of the battery. The MOS power transistors each has a source region, a well region and a drain region. A high resistance connected with either a parasitic diode on the side connected with the source generated between the source region and well region or a parasitic diode on the side connected with the drain generated between the drain region and well region in parallel is formed in the MOS power transistors.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: March 4, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Atsushi Umeda, Norihito Tokura, Hirohide Sato
  • Patent number: 5543703
    Abstract: A vehicular generator motor performing generator operation and motor operation is disclosed. The generator motor comprises an AC-DC converter means and a switching means. The converter means is composed of a plurality of MOSFETs and connected between each armature coil and a vehicular storage battery. Alternating current produced across the coils is converted into a direct current for charging the battery by the AC-DC converter means in generator operation mode. In motor operation mode, the DC output from the battery is converted into an alternating current for setting up a rotating magnetic field by the converter means, and the battery output is fed to the armature coils. The mode of operation of the MOSFETs is switched between these two modes by the switching means. The rotating field produces a certain phase difference with the magnetic field developed by the rotating magnetic poles. The MOSFETs are made of SiC having a smaller resistivity than that of Si.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: August 6, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shin Kusase, Kenzo Mitani, Atsushi Umeda, Norihito Tokura, Hirohide Sato
  • Patent number: 5519245
    Abstract: An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: May 21, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Norihito Tokura, Naoto Okabe, Naohito Kato
  • Patent number: 5504360
    Abstract: A vertical type semiconductor device is provided with an improved construction which greatly decreases the on-resistance without impairing the breakdown voltage thereof. In the fundamental DMOS cells that control a current to constitute the vertical semiconductor device, through-hole cells are arranged along the sides of a cell having a channel. The through-hole cell includes a through-hole extending from the surface of an n.sup.- -type drift region toward an n.sup.+ -type drain region, and also includes an n.sup.+ -type through-hole region that is formed by diffusing impurities from the inner wall of the through-hole which is continuous with the n.sup.+ -type drain region. A breakdown voltage of the element is maintained by the n.sup.- -type drift region between a p-type well region and the n.sup.+ -type through-hole region or the n.sup.+ -type drain region.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: April 2, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Norihito Tokura, Kunihiko Hara
  • Patent number: 5460985
    Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: October 24, 1995
    Assignee: Ipics Corporation
    Inventors: Norihito Tokura, Shigeki Takahashi
  • Patent number: 5453390
    Abstract: A power semiconductor device having current detecting function comprising a detection pert that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: September 26, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Toshiaki Nishizawa, Akira Kuroyanagi, Tsuyoshi Yamamoto, Norihito Tokura
  • Patent number: 5448092
    Abstract: An insulated gate bipolar transistor (IGBT) element has a current detection function. An impurity-diffused area is formed at an area different from a unit cell area on the surface of the element. The current detection is performed by detecting a voltage drop due to carriers flowing in the lateral resistance of the impurity-diffused area. For example, in an n-channel IGBT, electrons are injected from a source electrode through an n-type source layer and the channel to an n-type drain layer at the cell when the unit cell is in an on-state. The pn junction at the drain side is forwardly biased to inject holes from the p-type drain layer to the n-type drain layer. At this time, the electrons also flow to the lower side of the p-type impurity-diffused area provided as the detection portion. Thus, the hole injection occurs at this portion. These surplus holes are discharged through the p-type layer of the detection portion to the source electrode.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: September 5, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Naoto Okabe, Norihito Tokura
  • Patent number: 5365085
    Abstract: A power semiconductor device constituted of a MOSFET incorporating a current detecting function for detecting current making use of a voltage drop developed across a channel resistance in which variations in the channel resistance due to its temperature and the gate voltage are compensated for and thereby highly accurate current detection is achieved.
    Type: Grant
    Filed: July 29, 1991
    Date of Patent: November 15, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Norihito Tokura, Tsuyoshi Yamamoto
  • Patent number: 4985743
    Abstract: This invention is basically related to an insulated gate bipolar transistor comprising a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer formed on the substrate and having a low concentration of impurities, a first conductivity type base layer formed on a surface of the semiconductor layer, a second conductivity type source layer formed on the surface of the base layer and having a channel region at at least one end thereof, a gate electrode, a source electrode and a drain electrode, and is characterized in that a voltage dropping portion is provided either inside the source layer or between the source layer and the source electrode. Accordingly an insulated gate bipolar semiconductor transistor having this configuration can prevent a latch up phenomenon caused by a voltage drop in a source layer.
    Type: Grant
    Filed: July 19, 1988
    Date of Patent: January 15, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Norihito Tokura, Hiroyasu Ito, Naoto Okabe
  • Patent number: 4962411
    Abstract: A semiconductor device with a current detecting function in which in place of an external resistor for detecting an operation current such as drain current or collector current of a device such as an FET or bipolar transistor, a probe electrode is formed in proximity to the device depletion layer to connect therethrough with the device channel to generate a probe voltage corresponding to the operation current.
    Type: Grant
    Filed: February 3, 1989
    Date of Patent: October 9, 1990
    Assignee: Nippondenso Co., Ltd.
    Inventors: Norihito Tokura, Hironari Kuno, Hiroyasu Ito, Hirohiko Saito, Kunihiko Hara
  • Patent number: 4739183
    Abstract: Disclosed is a local area network for a vehicle which comprises a plurality of terminal stations each having an input/output port for various signals, a main-loop formed by series connection of the terminal stations and transmission lines, a sub-loop arranged in parallel to the main-loop and formed by series connection of the terminal stations and transmission lines, and controllers. One of the terminal stations receives a large amount of information such as an audio signal from an audio transmitter and one of the other terminal stations supplies a large amount of information such as an audio signal to an audio receiver.
    Type: Grant
    Filed: July 24, 1986
    Date of Patent: April 19, 1988
    Assignee: Nippon Soken, Inc.
    Inventors: Norihito Tokura, Hisasi Kawai