Abstract: A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

Abstract: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity-type region, a second conductivity-type source region, a gate insulating film and a gate electrode. The first conductivity-type region is provided in an upper layer portion of the semiconductor substrate. The second conductivity-type source region and a second conductivity-type drain region are arranged by being separated from each other in an upper layer portion of the first conductivity-type region. The gate insulating film is provided on the semiconductor substrate. The gate electrode is provided on the gate insulating film. An effective concentration of impurities in a channel region corresponding to a region directly below the gate electrode in the first conductivity-type region has a maximum at an interface between the gate insulating film and the channel region, and decreases toward a lower part of the channel region.

Abstract: A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.

Abstract: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, an element isolation insulator, a source layer of a second conductivity type, a drain layer of the second conductivity type, a contact layer of the first conductivity type and a gate electrode. The element isolation insulator is formed on the semiconductor substrate. The source layer is formed on the semiconductor substrate and is in contact with a side surface of the element isolation insulator. The drain layer is formed on the semiconductor substrate, is in contact with the side surface, and is spaced from the source layer. The contact layer is formed between the source layer and the drain layer. The gate electrode is provided on the element isolation insulator along the side surface.

Abstract: According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first source portion, a second source portion, a drain portion, a first main electrode, a second main electrode, and a gate electrode. The first source portion includes a first source contact region of a second conductivity type and a back gate contact region of the first conductivity type. The drain portion includes a drain contact region of the second conductivity type, a first drift region of the second conductivity type, and a second drift region of the second conductivity type. When a reverse bias is applied to p-n junction between the semiconductor layer and the drain portion, avalanche breakdown is more likely to occur near the first drift region than near the second drift region.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

Abstract: A semiconductor device, includes: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type, the second semiconductor region having a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the first semiconductor region; a source region of a second conductivity type provided on the first semiconductor region; a drain region of the second conductivity type provided on the second semiconductor region; an insulating film provided on the semiconductor layer between the source region and the drain region; a gate electrode provided on the insulating film; and a drift region of the second conductivity type provided in a surface side portion of the semiconductor layer between the gate electrode and the drain region, the drift region being in contact with the drain region and having a second conductivity type impurity concentration lower than a second conductivity type

Abstract: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

Abstract: A semiconductor device includes: a semiconductor region of first conductivity type provided in a semiconductor layer of first conductivity type; a first semiconductor region of second conductivity type; a second semiconductor region of second conductivity type; a third semiconductor region of second conductivity type having a lower impurity concentration than the second semiconductor region of second conductivity type; a first insulating layer provided in the third semiconductor region of second conductivity type; a control electrode provided on the semiconductor region of first conductivity type via a second insulating layer; a first auxiliary electrode provided on the first insulating layer; a first main electrode electrically connected to the first semiconductor region of second conductivity type; and a second main electrode electrically connected to the second semiconductor region of second conductivity type.

Abstract: A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

Abstract: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

Abstract: A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.

Abstract: A semiconductor device includes: a high-side switching element having a first switching element connected between an input voltage line and an inductive load; and a low-side switching element having a second switching element and a third switching element that are connected in parallel between the inductive load and a reference voltage line. A surge current is discharged through the third switching element to the reference voltage line when a surge is applied to a terminal connected to the inductive load in the low-side switching element.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

Abstract: A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

Abstract: A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.