Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

Abstract: A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: A semiconductor device comprises a semiconductor substrate; a semiconductor layer having a higher resistance than that of said semiconductor substrate and provided on a top surface of said semiconductor substrate; a gate electrode provided on a gate insulating film on the top surface of said semiconductor layer; a drain layer of a first conductivity type selectively provided in a location in said semiconductor layer in one side of said gate electrode; a drain electrode connected to said drain layer; a source layer of the first conductivity type selectively provided in a location in said semiconductor layer in the other side of said gate electrode; an element-side connecting portion selectively provided on said semiconductor layer, which does not reach a channel portion between said source layer and said drain layer of said semiconductor layer and also does not reach to said semiconductor substrate, and which is in contact with said source layer and has lower resistance than that of said semiconductor layer; a

Abstract: A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

Abstract: A plurality of trenches are formed in a drift region between a p-type body region and an-type buffer region. A silicon oxide film is formed on the side and bottom of each of the trenches, and an SIPOS film is buried into each of the trenches. The trenches are formed by RIE, and the SIPOS film is deposited by LPCVD and an undesired portion can be removed by dry etching such as RIE. The SIPOS film is connected to a source electrode at the source end of each trench, and it is connected to a drain electrode directly or through a resistor at the drain end thereof. When a high voltage is applied, a depletion layer expands in the n-type drift region from an interface between the n-type drift region and the trench on each side of the n-type drift region, therefore, the impurity concentration of the n-type drift region can be heightened without lowering the high breakdown voltage, and the resistance of the drift region can be decreased.

Abstract: A high breakdown voltage semiconductor device comprising a first base region of a first conductivity type, a second base region of a second conductivity type, which is formed in a surface region of the first base region, a first gate insulation film formed on an inner wall of a first LOCOS groove formed passing through the second base region to reach the first base region, a first gate electrode formed on the first gate insulation film, a first source region of a first conductivity type, which is formed in a surface region of the second base region around the first LOCOS groove in such a manner as to contact with the first gate insulating film, a first drain region formed in a surface region of the first base region in such a manner as to be spaced apart from the second base region, a source electrode formed on the first source region and on the second base region, and a drain electrode formed on the first drain region.

Abstract: An n-type buffer layer and a p-type base layer are formed in the surface of the n.sup.- -type drift layer. A p.sup.+ -type drain layer is formed in the surface of the n-type buffer layer. An n.sup.+ -type source layer and a p.sup.+ -type contact layer are formed in the surface of the p-type base layer. A main gate electrode is arranged to face, through a gate oxide film, a surface of the p-type base layer which is interposed between the n.sup.+ -type source layer and the n.sup.- -type drift layer. An n-type relay layer is formed in the surface of the n.sup.- -type drift layer to face the n.sup.+ -type source layer through the p-type base layer under the main gate electrode. The n-type relay layer extends from the n.sup.- -type drift layer into the p-type base layer. The n-type relay layer decreases the channel resistance.

Abstract: A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer form

Abstract: A lateral IGBT has a n-source layer and a p-contact layer both in contact with a source electrode. The source layer has a trunk adjacent to a channel region under a gate electrode, and a plurality of branches extending from its trunk to the source electrode to be in contact with the source electrode. The contact layer has a trunk in contact with the source electrode, and a plurality of branches extending from its trunk to the source layer trunk The source layer branches and the contact layer branches have shapes complementary with each other and are alternately arranged. The source layer trunk has a width La in an X direction (channel direction), which satisfies a condition, 0.5 .mu.m<La<2 .mu.m.

Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.

Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.