Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

Abstract: A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

Abstract: A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.

Abstract: A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

Abstract: A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

Abstract: A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first

Abstract: A gate electrode is formed on a gate insulator above a semiconductor substrate. Diffused regions are formed in a surface of the semiconductor substrate as sandwiching the gate electrode therebetween. A high-resistance layer is formed in the surface of the semiconductor substrate as electrically connected to the diffused region. A low-resistance layer is formed in the surface of the semiconductor substrate as electrically connected to the high-resistance layer. A drain electrode is connected to the low-resistance layer.

Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

Abstract: A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

Abstract: A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

Abstract: A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

Abstract: A semiconductor device comprises a semiconductor substrate; a semiconductor layer having a higher resistance than that of said semiconductor substrate and provided on a top surface of said semiconductor substrate; a gate electrode provided on a gate insulating film on the top surface of said semiconductor layer; a drain layer of a first conductivity type selectively provided in a location in said semiconductor layer in one side of said gate electrode; a drain electrode connected to said drain layer; a source layer of the first conductivity type selectively provided in a location in said semiconductor layer in the other side of said gate electrode; an element-side connecting portion selectively provided on said semiconductor layer, which does not reach a channel portion between said source layer and said drain layer of said semiconductor layer and also does not reach to said semiconductor substrate, and which is in contact with said source layer and has lower resistance than that of said semiconductor layer; a

Abstract: A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: A semiconductor device includes a second conductivity type layer selectively formed by changing impurity concentrations on a semiconductor substrate, a first conductivity type source region formed on the second conductivity type layer, a first conductivity type drain region formed on the second conductivity type layer apart from the first conductivity type source region, a gate electrode formed between the first conductivity type source region and the first conductivity type drain region across an insulation film, and a second conductivity type contact layer formed adjacent to the first conductivity type source region, wherein the second conductivity type layer in the source region side has a higher impurity concentration than the impurity concentration of the second conductivity type layer in the drain region side.

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.

Abstract: A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

Abstract: A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.