Abstract: A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page.

Abstract: A storage controller interface includes, on a disk controller side of the storage controller interface, a first transceiver circuit configured to transfer a first block of user data to a read channel during a write operation, and a gate transmit circuit configured to, subsequent to the first block of user data being transferred, assert a gate signal to flush the first block of user data from the read channel. The storage controller interface further includes, on a read channel side of the storage controller interface, a second transceiver circuit configured to receive the first block of user data, a gate receive circuit configured to receive the gate signal, and a write fault transceiver circuit configured to selectively assert a write fault signal if the gate transmit circuit does not assert the gate signal subsequent to the first block of user data being transferred to the read channel.

Abstract: Aspects of the disclosure provide a method for driving dimmable load. The method includes detecting a dimming characteristic in an energy source from which a load draws a first energy according to the dimming characteristic. The dimming characteristic requires a second energy in addition to the first energy to be drawn from the energy source to sustain an operation of the energy source. The method further includes biasing a switch to consume the second energy. The second energy and the first energy are drawn from the energy source to sustain the operation of the energy source.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell.

Abstract: Aspects of the disclosure provide a method for driving dimmable load. The method includes detecting a dimming characteristic in an energy source from which a load draws a first energy according to the dimming characteristic. The dimming characteristic requires a second energy in addition to the first energy to be drawn from the energy source to sustain an operation of the energy source. The method further includes biasing a switch to consume the second energy. The second energy and the first energy are drawn from the energy source to sustain the operation of the energy source.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: A light emitting diode (LED) lighting system includes a first string of first LEDs emitting light having a first color. A second string of second LEDs emits light having a second color and connected in series with the first string of first LEDs; A first switch and a second switch are connected in series. A regulator module is configured to modulate the first switch and the second switch to provide a desired current ratio. The desired current ratio corresponds to a ratio of a first current through the first string of first LEDs to a second current through the second string of second LEDs.

Abstract: A system-on-chip including an ingress arbiter module to receive a plurality of service requests from a plurality of devices located upstream to access a resource located downstream. Each of the service requests includes a quality of service value and a first timing budget value specified by the respective device to indicate an amount of time in which the respective service request is to be serviced by the resource. The ingress arbiter module selects a first service request based on the quality of service values, the first timing budget values, and a time delay associated with arbitrating the plurality of service requests and outputting the first service request downstream. A timing budget generator module generates a second timing budget value for the first service request based on the first timing budget value associated with the first service request, and the time delay.

Abstract: An apparatus includes a first LED driver configured to control a first string of LEDs, a second LED driver configured to control a second string of LEDs, a third LED driver configured to control a third string of LEDs, and a control circuit configured to receive a control signal and to control the first, second, and third LED drivers so that the first, second, and third strings of LEDs cooperate in producing light according to the control signal and a color curve.

Abstract: A system including a first filter. The first filter includes first taps that receive respective coefficients. The first filter, based on the coefficients, filters an input signal. A first device updates some of the coefficients based on the input signal. The first device does not update one of the coefficients. A second filter includes second taps configured to receive respectively first and second coefficients. The second filter, based on the first and second coefficients, filters an output of the first filter. A second device, based on the output of the first filter, updates the second coefficient to account for a change in: an amount of gain of the system not accounted for by the first device due to the one of the coefficients not being updated; and a timing phase error of the input signal as a result of the first device not updating the one of the coefficients.

Abstract: A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell.

Abstract: A resistive random access memory system includes a plurality of bitlines, a plurality of wordlines, and an array of resistive random access memory cells. Each of the resistive random access memory cells in the array includes a transistor and a resistive random access memory element connected in a common gate configuration.

Abstract: A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values. The one or more of the interference values are selected based on (i) the state to which the memory cell is to be programmed, and (ii) the states of the one or more memory cells.

Abstract: Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.

Abstract: A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory.

Abstract: Systems, methods, and other embodiments associated with a detector that processes signals read from a storage device are described. According to one embodiment, the detector includes a signal estimator configured to generate an estimate of a control signal by determining characteristics of the control signal from a read signal. The read signal includes the data signal and the control signal embedded together. The signal estimator is configured to generate the estimate of the control signal as a function of the characteristics. The detector includes a cancellation unit configured to produce the data signal by cancelling the estimate of the control signal from the read signal.

Abstract: Aspects of the disclosure provide a method. The method includes detecting a dimming characteristic in an energy source that provides energy to be transferred to a load via a magnetic component, receiving a dimming control signal, and controlling a switch in connection with the magnetic component based on the dimming characteristic and the dimming control signal to transfer energy to the load via the magnetic component.

Abstract: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface.

Abstract: A memory controller provides error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to identify an ECC protection level from a plurality of ECC protection levels for data that is to be stored in the memory device, generate ECC data for the data that is to be stored in the memory device using an ECC corresponding to the identified ECC protection level, store the generated ECC data in the cache, and store the data in the memory device.