Abstract: A control module for controlling a solid-state disk (SSD) includes a first interface, a cache memory, and a second interface. The first interface interfaces a nonvolatile semiconductor memory (NVM) of the SSD to a processor that is located externally to the SSD. The cache memory selectively caches at least one of code and data from the NVM. The second interface interfaces the cache memory to the processor and outputs portions of at least one of code and data from the cache memory to the processor.

Abstract: A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory.

Abstract: A system includes a transformer. The transformer includes a first coil and a second coil. The first coil is configured to receive a first voltage based on an output of a switching circuit. The second coil is configured to generate a first current based on the first voltage to power a solid-state load. The system also includes a third coil. The third coil is configured to generate a second voltage based on the first voltage.

Abstract: A first power management module includes a power management interface to communicate with a power management bus and manages power states of a first device communicating with a system bus. The power management interface includes a first interface to communicate a first control signal to transition the first device from a first power state to a second power state, a second interface to communicate a second control signal to turn on or off a power supply to the first device, and a third interface to communicate a third control signal to turn on or off a clock of the first device. A second power management module manages power consumption of the first device, independently of a second device communicating with the system bus, based on the power states of the first device using one or more of the first control signal, the second control signal, and the third control signal.

Abstract: Systems, methods, and other embodiments associated with a data detector that processes signals read from a storage device are described. According to one embodiment, a detector for detecting a data signal embedded in a read signal from a storage device includes a signal estimator configured to generate an estimate of the control signal from the read signal by sampling the read signal to determine characteristics of the control signal. The read signal includes the data signal and the control signal. The signal estimator uses the characteristics to calculate the estimate of the control signal. The detector also includes a cancellation unit configured to produce the data signal by cancelling the estimate of the control signal from the read signal.

Abstract: A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals.

Abstract: Methods, software, and apparatuses for reading from and/or writing to an optical storage medium. The methods generally include steps for reading a region of an optical storage medium to produce a readback signal, processing predetermined pattern data to produce one or more measurement instructions, measuring one or more characteristics of the readback signal in response to the measurement instructions to produce one or more measurement results, and further processing the readback signal in accordance with one or more of the measurement results. Thus, the ability to flexibly set test parameters and to quickly and accurately test the write characteristics of a recordable or re-writable optical storage medium is provided.

Abstract: Aspects of the disclosure provide a circuit that includes a detection circuit and a controller. The detection circuit is configured to detect a starting of a conduction in a power supply provided via an electronic transformer. The controller is configured to control a current regulating circuit to pull a current from the electronic transformer at a pre-determined level during a time duration following the starting of the conduction, and pull the current at a reduced level according to a pre-determined profile after the time duration.

Abstract: A method of operating a mass storage device including caching data in a nonvolatile semiconductor memory, in which the nonvolatile semiconductor memory has a predetermined usable lifetime. The method includes iteratively performing an operation on the nonvolatile semiconductor memory until the nonvolatile semiconductor memory reaches a predetermined state, wherein the operation includes an erase operation or a program operation; and determining an extent to which the nonvolatile semiconductor memory has degraded in response to a number of iterations of the operation required for the nonvolatile semiconductor memory to reach the predetermined state. The method also includes determining whether the nonvolatile semiconductor memory has reached the predetermined usable lifetime in response to the extent to which the nonvolatile semiconductor memory has degraded.

Abstract: Methods and systems for storing data in a memory system with different levels of redundancy are disclosed. Methods and systems consistent with the present invention provide allow a redundancy level to be associated with received data, wherein associating the redundancy level of the data includes determining a desired level of protection for that data and determining the redundancy level based on the desired level of protection. A zone within a memory system is located that has a redundancy level that matches the redundancy level of the data, and the data is stored in the located zone with the desired redundancy level.

Abstract: A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells. Each of the memory cells is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of a first bit line of the bit lines and a first word line of the word lines. The second memory cell is located at the intersection of a second bit line of the bit lines and a second word line of the word lines. The read/write module is configured to concurrently activate the first memory cell and the second memory cell to simultaneously access both the first memory cell and the second memory cell.

Abstract: A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory.

Abstract: A system includes a voltage sensing module and a frequency adjustment module. The voltage sensing module is configured to sense a supply voltage of a circuit block, generate a first control signal when the supply voltage is less than or equal to a first voltage, and generate a second control signal when the supply voltage is within a predetermined range of a second voltage. The frequency adjustment module is configured to set a frequency of a clock signal supplied to the circuit block to less than a normal operating frequency of the circuit block when the supply voltage is initially supplied to the circuit block after a power on reset operation and the first control signal or the second control signal is received.

Abstract: According to an aspect of the present disclosure, a system for correcting for DC characteristics of a magnetic recording system includes: circuitry implementing at least a portion of a write channel of the magnetic recording system; and circuitry configured to process output data of the write channel circuitry in accordance with a read channel of the magnetic recording system and repeatedly trigger re-writing through the write channel circuitry using different ones of a plurality of available data scramblings until a measured baseline wander exceeds a target threshold.

Abstract: A magnetic storage system includes a read and write device that (i) magnetically writes data on a platter, and (ii) reads, via a read element, the data written magnetically on the platter. The read element includes a first terminal and a second terminal. A transistor includes a gate. The transistor is closed responsive to the gate not receiving power. Responsive to the gate of the transistor receiving power, the transistor provides an open circuit between the first terminal and the second terminal. Responsive to the gate of the transistor not receiving power, the transistor shorts the first terminal to the second terminal. A first limiting circuit limits a first voltage of (i) the transistor and (ii) the first terminal. A second limiting circuit limits a second voltage of (i) the transistor and (ii) the second terminal.

Abstract: A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells.

Abstract: A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory.

Abstract: An integrated circuit includes a first memory, a second memory, a processor, and a descrambler. The first memory is configured to store a key. The first memory is a one-time-programmable memory. The processor is configured to: determine whether the first memory has been programmed; and in response to the first memory not having been programmed, (i) load firmware from a third memory into the second memory, and (ii) execute the firmware. The third memory is separate from the integrated circuit. The processor is also configured to, in response to the first memory having been programmed, load the firmware from the third memory into the second memory. The descrambler is configured to, in response to the first memory having been programmed, descramble the firmware based on the key.

Abstract: A system including a memory controller configured to identify a first memory cell of a first plurality of memory cells as defective and to store information about the first memory cell in a second memory cell of a second plurality of memory cells. The second plurality of memory cells is configured to store data at a lower density than the first plurality of memory cells. In response to (i) reading data from the first plurality of memory cells and (ii) the first memory cell of the first plurality of memory cells having been identified as defective, the memory controller is configured to read the information about the first memory cell stored in the second memory cell and to determine a location of the first memory cell in the first plurality of memory cells.

Abstract: A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell, and store the interference values. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values.