Abstract: A system includes a first light emitting diode configured to produce light of a first color and a second light emitting diode configured to produce light of a second color. A constant current circuit is configured to provide a first current, wherein (i) the first current is approximately constant, (ii) a first portion of the first current flows through the second light emitting diode, and (iii) a remaining portion of the first current flows through the first light emitting diode. A current regulating circuit is configured to control the first portion of the first current flowing through the second light emitting diode. The current regulating circuit is connected in series with the second light emitting diode, the constant current circuit, and a reference potential. The first light emitting diode is connected in series directly between the constant current circuit and the reference potential.

Abstract: A method includes: writing data in a magnetic recording system using a write channel of the magnetic recording system; processing output data of the write channel in accordance with a read channel of the magnetic recording system to measure baseline wander; and triggering re-writing through the write channel using different data scramblings when the measured baseline wander fails to satisfy a criterion. The processing can include modeling the read channel of the magnetic recording system, modeling one or more high pass filtering circuits of the magnetic recording system, or both. The writing can include encoding the data after scrambling of the data, the processing can include using a discrete time model of DC offset in the magnetic recording system, and the triggering can include triggering re-writing through the write channel using different scrambling seeds when the measured baseline wander fails to exceed a threshold.

Abstract: A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.

Abstract: A resistive element of a resistive memory cell. The resistive element includes a contact in communication with a substrate. A bottom electrode is formed on the contact. A transitional metal oxide layer is formed on the bottom electrode. The transitional metal oxide layer includes oxygen vacancies configured to receive donor oxygen atoms. A transition layer formed on the transitional metal oxide layer includes donor oxygen atoms. A reactive metal layer is formed on the transition layer. A top electrode is formed on the transitional metal oxide layer. The transition layer is configured to provide the donor oxygen atoms to the transitional metal oxide layer in response to a voltage being applied to the top electrode.

Abstract: A controller for a buck regulator for a lighting system including light emitting diodes includes a voltage control loop configured to compare a voltage reference and a feedback voltage. The feedback voltage is based upon a DC supply voltage to the controller. A voltage regulator is configured to receive an output of the voltage control loop and to generate a current reference. A current control loop is configured to receive a feedback current and to compare the current reference to the feedback current. A current regulator is configured to receive an output of the current control loop. A pulse width modulation circuit is configured to receive an output of the current regulator and to generate drive signals for first and second switches of the buck regulator.

Abstract: A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.

Abstract: A method including: forming a stack of resistive layers; prior to or subsequent to forming the stack of resistive layers, forming a conductive layer; applying a mask layer on the stack of resistive layers or the conductive layer; forming a first spacer on the mask layer; and etching away a first portion of the mask layer using the first spacer as a first mask to provide a remainder. The method further includes: forming a second spacer on the stack of the resistive layers or the conductive layer and the remainder of the mask layer; etching away a second portion of the remainder of the mask layer to form an island; and using the island as a second mask, etching the stack of the resistive layers to form a resistive element of a memory, and etching the conductive layer to form a conductive element of the memory.

Abstract: A system configured to provide current to power a solid-state light emitting diode in accordance with a dimming level, wherein the dimming level corresponds to an amount of light provided from the solid-state light emitting diode. The system includes a transformer and a switch. The transformer includes a coil. The transformer is configured to receive a first current. The coil is configured to, based on the first current, output a second current to power the solid-state light emitting diode. The switch is configured to, based on a dimming level that corresponds to the amount of light provided from the solid-state light emitting diode of the system, bleed a portion of the second current out of the coil to a ground reference in order to divert the portion of the second current from being supplied to the solid-state light emitting diode.

Abstract: A control module includes an encoder module, a detector module, a mapping module, and a difference module. The encoder module receives data, and based on the data, generates a first code word for drives. The drives are associated with a storage system. The detector module detects an addition of a second drive. The encoder module generates a second code word for the second drive. The mapping module: maps physical locations of the data in the drives to logical locations of the first code word; assigns a predetermined value to a logical location corresponding to an unused logical location; and based on the predetermined value, assigns the unused logical location to the second drive. The difference module generates a third code word based on each of the first and second code words. The encoder module, based on the first and third code words, generates a fourth code word for all drives.

Abstract: A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells.

Abstract: A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell.

Abstract: A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction.

Abstract: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface.

Abstract: A method of creating an on-chip capacitor includes: arranging, within a first layer, a first layer first polarity conducting strip adjacent to and spaced apart from a first layer second polarity conducting strip; arranging, within a second layer, a second layer first polarity conducting strip adjacent to and spaced apart from a second layer second polarity conducting strip, wherein the second layer second polarity conducting strip overlies the first layer second polarity conducting strip, and the second layer first polarity conducting strip overlies the first layer first polarity conducting strip; electrically connecting the first layer first-polarity conducting strip with the second layer first polarity conducting strip; and electrically connecting the first-layer second polarity conducting strip with the second layer second-polarity conducting strip.

Abstract: Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.

Abstract: Methods and apparatuses directed to high density holes and metallization are described herein. A method may include providing a dielectric layer including a plurality of holes, forming a fill material over a top surface of the dielectric layer and in the plurality of holes, and reflowing the fill material to substantially remove any voids in the plurality of holes. Other embodiments are also described.

Abstract: A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.

Abstract: A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells.